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    Bulk substrate FET integrated on CMOS SOI
    1.
    发明授权
    Bulk substrate FET integrated on CMOS SOI 有权
    集成在CMOS SOI上的散装衬底FET

    公开(公告)号：US08232599B2

    公开(公告)日：2012-07-31

    申请号：US12683456

    申请日：2010-01-07

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L27/1207 ,  H01L21/84

    摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
    2.
    发明申请
    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
    集成在CMOS SOI上的基极FET

    公开(公告)号：US20120187492A1

    公开(公告)日：2012-07-26

    申请号：US13425681

    申请日：2012-03-21

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/1207 ,  H01L21/84

    摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON
    6.
    发明申请
    POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON 审中-公开
    通过在多晶硅化学气相沉积期间在气相中添加污染物进行聚合工程

    公开(公告)号：US20090269926A1

    公开(公告)日：2009-10-29

    申请号：US12110594

    申请日：2008-04-28

    申请人： Abhishek Dube ,  Ashima B. Chakravarti ,  Anthony I. Chou ,  Wei He ,  Dominic J. Schepis

    发明人： Abhishek Dube ,  Ashima B. Chakravarti ,  Anthony I. Chou ,  Wei He ,  Dominic J. Schepis

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28035 ,  H01L29/4925

    摘要： A method of forming at least one gate conductor of a complementary metal oxide semiconductor performs a chemical vapor deposition process of polysilicon over a surface where a polysilicon gate is to be located. This deposition can be performed through a mask to form gate structures directly, or a later patterning process can pattern the polysilicon into gate structures. During the chemical vapor deposition process, the method adds impurities in the chemical vapor deposition process to optimize the grain size of the polysilicon according to a number of different methods.

    摘要翻译： 形成互补金属氧化物半导体的至少一个栅极导体的方法在多晶硅栅极位于的表面上进行多晶硅的化学气相沉积处理。 该沉积可以通过掩模进行直接形成栅极结构，或者后来的图案化工艺可以将多晶硅图案化成栅极结构。 在化学气相沉积过程中，该方法根据多种不同的方法在化学气相沉积工艺中添加杂质以优化多晶硅的晶粒尺寸。

    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process
    7.
    发明授权
    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process 失效

    公开(公告)号：US07491964B2

    公开(公告)日：2009-02-17

    申请号：US10905683

    申请日：2005-01-17

    申请人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

    发明人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481

    摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.

    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES
    10.
    发明申请
    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES 审中-公开
    用于减少前浇口结构中顶部止点效应的方法

    公开(公告)号：US20080188089A1

    公开(公告)日：2008-08-07

    申请号：US11671668

    申请日：2007-02-06

    申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    IPC分类号： H01L21/31

    CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

    摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

    摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。