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    Local oxidation of silicon planarization for polysilicon layers under thin film structures
    1.
    发明授权
    Local oxidation of silicon planarization for polysilicon layers under thin film structures 有权
    在薄膜结构下多晶硅层的硅平面化的局部氧化

    公开(公告)号：US07981759B2

    公开(公告)日：2011-07-19

    申请号：US11776116

    申请日：2007-07-11

    申请人： Andrew Cervin-Lawry ,  Mircea Capanu

    发明人： Andrew Cervin-Lawry ,  Mircea Capanu

    IPC分类号： H01L21/20

    CPC分类号： H01G4/33 ,  H01G4/40 ,  H01G7/00 ,  H01L28/60

    摘要： In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portions of the polysilicon film for a first amount of time; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that defines the patterned polysilicon layer; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon layer have about the same thickness and form a planar surface.

    摘要翻译： 根据本文所述的教导，用于制造具有平坦表面的图案化多晶硅层的方法可以包括以下步骤：在衬底材料上沉积多晶硅膜; 在所述多晶硅膜上沉积耐氧化掩模; 图案化和蚀刻所述耐氧化掩模以在所述多晶硅膜上形成图案化掩模层，使得所述多晶硅膜包括掩模和未掩模部分; 蚀刻多晶硅膜的未掩模部分第一时间; 将蚀刻的多晶硅膜氧化第二时间量以形成限定图案化多晶硅层的氧化物层; 并去除图案化的掩模层; 其中选择第一和第二时间量使得氧化物层和图案化多晶硅层具有大致相同的厚度并形成平坦表面。

    Low loss thin film capacitor and methods of manufacturing the same
    2.
    发明申请
    Low loss thin film capacitor and methods of manufacturing the same 审中-公开
    低损耗薄膜电容器及其制造方法

    公开(公告)号：US20060274476A1

    公开(公告)日：2006-12-07

    申请号：US11396447

    申请日：2006-04-03

    申请人： Andrew Cervin-Lawry ,  Mircea Capanu ,  Ivoyl Koutsaroff ,  Marina Zelner ,  Thomas Bernacki

    发明人： Andrew Cervin-Lawry ,  Mircea Capanu ,  Ivoyl Koutsaroff ,  Marina Zelner ,  Thomas Bernacki

    IPC分类号： H01G4/228

    CPC分类号： H01L23/5223 ,  H01G4/33 ,  H01G4/40 ,  H01L27/016 ,  H01L28/55 ,  H01L28/65 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In accordance with the teachings described herein, low loss thin film capacitors and methods of manufacturing the same are provided. A low loss thin-film capacitor structure may include first and second electrodes and a polar dielectric between the first and second electrodes. The polar dielectric and the first and second electrodes collectively form a capacitor having an operational frequency band. The capacitor structure may also include one or more layers that affect the acoustic properties of the thin-film capacitor structure such that the capacitor absorbs RF energy at a frequency that is outside of the operational frequency band. A method of manufacturing a low loss thin-film capacitor may include the steps of fabricating a capacitor structure that includes a polar dielectric material, and modifying the acoustic properties of the capacitor structure such that the polar capacitor absorbs RF energy at a frequency that is outside of the operating frequency band of the capacitor structure.

    摘要翻译： 根据本文所述的教导，提供了低损耗薄膜电容器及其制造方法。 低损耗薄膜电容器结构可以包括第一和第二电极以及第一和第二电极之间的极性电介质。 极性电介质和第一和第二电极共同形成具有工作频带的电容器。 电容器结构还可以包括影响薄膜电容器结构的声学特性的一个或多个层，使得电容器以在工作频带之外的频率吸收RF能量。 制造低损耗薄膜电容器的方法可以包括制造包括极性介电材料的电容器结构的步骤，并且改变电容器结构的声学特性，使得极性电容器以在外部的频率吸收RF能量 的电容器结构的工作频带。

    Electrostrictive resonance suppression for tunable capacitors
    4.
    发明授权
    Electrostrictive resonance suppression for tunable capacitors 有权
    用于可调谐电容器的电致伸缩共振抑制

    公开(公告)号：US08194387B2

    公开(公告)日：2012-06-05

    申请号：US12407802

    申请日：2009-03-20

    申请人： Mircea Capanu ,  Andrew Cervin-Lawry ,  Marina Zelner

    发明人： Mircea Capanu ,  Andrew Cervin-Lawry ,  Marina Zelner

    IPC分类号： H01G5/00 ,  H01G7/00

    CPC分类号： H01G5/38 ,  H01G7/02 ,  H01G7/06 ,  H01L27/016 ,  H01L27/0808 ,  H01L28/60

    摘要： A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

    摘要翻译： 多层电容器包括三个或更多个电容器层。 第一层包括第一DC偏置可调电容器。 声耦合到第一层的第二层包括第二DC偏置的可调电容器。 声耦合到第二层的第三层包括第三直流偏置可调电容器。 第一，第二和第三电容器的每个电介质具有在5％以内约相同频率的共振，并且第一，第二和第三电容器的内部电极具有大约相同频率的共振，在5％以内。 每个层的共振至少是厚度，密度和材料的函数。 第一，第二和第三层被偏置以产生破坏性声学干扰，并且多层电容器可在大于0.1GHz的频率下操作。

    Electrostrictive Resonance Suppression for Tunable Capacitors
    6.
    发明申请
    Electrostrictive Resonance Suppression for Tunable Capacitors 有权
    可调电容器的电致伸缩共振抑制

    公开(公告)号：US20100238602A1

    公开(公告)日：2010-09-23

    申请号：US12407802

    申请日：2009-03-20

    申请人： Mircea Capanu ,  Andrew Cervin-Lawry ,  Marina Zelner

    发明人： Mircea Capanu ,  Andrew Cervin-Lawry ,  Marina Zelner

    IPC分类号： H01G7/06

    CPC分类号： H01G5/38 ,  H01G7/02 ,  H01G7/06 ,  H01L27/016 ,  H01L27/0808 ,  H01L28/60

    摘要： A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

    摘要翻译： 多层电容器包括三个或更多个电容器层。 第一层包括第一DC偏置可调电容器。 声耦合到第一层的第二层包括第二DC偏置的可调电容器。 声耦合到第二层的第三层包括第三直流偏置可调电容器。 第一，第二和第三电容器的每个电介质具有在5％以内约相同频率的共振，并且第一，第二和第三电容器的内部电极具有大约相同频率的共振，在5％以内。 每个层的共振至少是厚度，密度和材料的函数。 第一，第二和第三层被偏置以产生破坏性声学干扰，并且多层电容器可在大于0.1GHz的频率下操作。

    Electrostrictive Resonance Suppression for Tunable Capacitors
    7.
    发明申请
    Electrostrictive Resonance Suppression for Tunable Capacitors 有权
    可调电容器的电致伸缩共振抑制

    公开(公告)号：US20120218733A1

    公开(公告)日：2012-08-30

    申请号：US13467641

    申请日：2012-05-09

    申请人： Mircea Capanu ,  Andrew Cervin-Lawry ,  Marina Zelner

    发明人： Mircea Capanu ,  Andrew Cervin-Lawry ,  Marina Zelner

    IPC分类号： H05K7/00

    CPC分类号： H01G5/38 ,  H01G7/02 ,  H01G7/06 ,  H01L27/016 ,  H01L27/0808 ,  H01L28/60

    摘要： A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

    摘要翻译： 多层电容器包括三个或更多个电容器层。 第一层包括第一DC偏置可调电容器。 声耦合到第一层的第二层包括第二DC偏置的可调电容器。 声耦合到第二层的第三层包括第三直流偏置可调电容器。 第一，第二和第三电容器的每个电介质具有在5％以内约相同频率的共振，并且第一，第二和第三电容器的内部电极具有大约相同频率的共振，在5％以内。 每个层的共振至少是厚度，密度和材料的函数。 第一，第二和第三层被偏置以产生破坏性声学干扰，并且多层电容器可在大于0.1GHz的频率下操作。

    Local Oxidation of Silicon Planarization for Polysilicon Layers Under Thin Film Structures
    8.
    发明申请
    Local Oxidation of Silicon Planarization for Polysilicon Layers Under Thin Film Structures 有权
    薄膜结构下多晶硅层的硅平面化局部氧化

    公开(公告)号：US20090017591A1

    公开(公告)日：2009-01-15

    申请号：US11776116

    申请日：2007-07-11

    申请人： Andrew Cervin-Lawry ,  Mircea Capanu

    发明人： Andrew Cervin-Lawry ,  Mircea Capanu

    IPC分类号： H01L21/02 ,  H01G4/20

    CPC分类号： H01G4/33 ,  H01G4/40 ,  H01G7/00 ,  H01L28/60

    摘要： In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portions of the polysilicon film for a first amount of time; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that defines the patterned polysilicon layer; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon layer have about the same thickness and form a planar surface.

    摘要翻译： 根据本文所述的教导，用于制造具有平坦表面的图案化多晶硅层的方法可以包括以下步骤：在衬底材料上沉积多晶硅膜; 在所述多晶硅膜上沉积耐氧化掩模; 图案化和蚀刻所述耐氧化掩模以在所述多晶硅膜上形成图案化掩模层，使得所述多晶硅膜包括掩模和未掩模部分; 蚀刻多晶硅膜的未掩模部分第一时间; 将蚀刻的多晶硅膜氧化第二时间量以形成限定图案化多晶硅层的氧化物层; 并去除图案化的掩模层; 其中选择第一和第二时间量使得氧化物层和图案化多晶硅层具有大致相同的厚度并形成平坦表面。

    Hermetic Passivation Layer Structure for Capacitors with Perovskite or Pyrochlore Phase Dielectrics
    9.
    发明申请
    Hermetic Passivation Layer Structure for Capacitors with Perovskite or Pyrochlore Phase Dielectrics 审中-公开
    具有钙钛矿或热解相电介质的电容器的密封钝化层结构

    公开(公告)号：US20080001292A1

    公开(公告)日：2008-01-03

    申请号：US11767559

    申请日：2007-06-25

    申请人： Marina Zelner ,  Paul Bun Cheuk Woo ,  Andrew Cervin-Lawry ,  Susan C. Nagy ,  Miroea Capanu

    发明人： Marina Zelner ,  Paul Bun Cheuk Woo ,  Andrew Cervin-Lawry ,  Susan C. Nagy ,  Miroea Capanu

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01G13/00 ,  H01L28/57

    摘要： A thin-film capacitor structure fabricated on a substrate is provided. The thin-film capacitor includes a pyrochlore or perovskite alkali earth dielectric layer between a plurality of electrode layers. A pyrochlore or perovskite hydrogen-gettering barrier layer is deposited over the thin-film capacitor. A hermetic seal layer is deposited over the barrier layer by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or some other hydrogen-producing method. The hydrogen-gettering barrier layer prevents hydrogen from reacting with and degrading the properties of the dielectric material, thereby enhancing the durability and other features of the capacitor.

    摘要翻译： 提供了在基板上制造的薄膜电容器结构。 薄膜电容器包括在多个电极层之间的烧绿石或钙钛矿碱土介电层。 在薄膜电容器上沉积烧绿石或钙钛矿吸氢阻挡层。 通过等离子体增强化学气相沉积（PECVD），低压化学气相沉积（LPCVD）或一些其它制氢方法，在阻挡层上沉积密封层。 吸氢阻挡层防止氢与介电材料的性质发生反应并降低其性能，从而提高电容器的耐久性和其它特征。