公开(公告)号：US10732976B2

公开(公告)日：2020-08-04

申请号：US14655122

申请日：2013-01-10

申请人： Alistair Robertson ,  Jeffrey W. Scott

发明人： Alistair Robertson ,  Jeffrey W. Scott

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50

摘要： A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode.

公开(公告)号：US20150356016A1

公开(公告)日：2015-12-10

申请号：US14759206

申请日：2013-01-11

申请人： ALISTAIR ROBERTSON ,  NANCY AMEDEO ,  MARK MAIOLANI

发明人： ALISTAIR ROBERTSON ,  NANCY AMEDEO ,  MARK MAIOLANI

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0862 ,  G06F9/30054 ,  G06F9/3802 ,  G06F9/3814 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0873 ,  G06F2212/461 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/7201

摘要： A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory [NVM] comprising a plurality of NVM lines. For each unconditional change of flow instruction in the executable code, the method comprises establishing a NVM line address of the NVM line containing said unconditional change of flow instruction; establishing a destination address associated with the unconditional change of flow instruction; determining whether the destination address is in an address range corresponding to a NVM-pre-fetch starting from said NVM line address; establishing a pre-fetch flag indicating whether the destination address is in the address range corresponding to a NVM-pre-fetch starting from said NVM line address; and recording the pre-fetch flag in a pre-fetch control information record. Also, a NVM controller, a device, a processor system and computer program products are described.

摘要翻译： 描述了从可执行代码建立预取控制信息的方法。 该方法包括：当从包括多个NVM线的非易失性存储器（NVM）检索可执行代码时，检查可执行代码以查找在执行可执行代码期间对应于程序流的无条件改变的一个或多个指令。 对于可执行代码中的每个无条件改变流程指令，该方法包括建立包含所述无条件流动指令改变的NVM行的NVM行地址; 建立与无条件改变流程指令相关联的目标地址; 确定所述目的地址是否处于从所述NVM行地址开始的NVM预取对应的地址范围内; 建立指示目的地地址是否在与从NVM线地址开始的NVM预取相对应的地址范围内的预取标志; 并将预取标志记录在预取控制信息记录中。 此外，还描述了NVM控制器，设备，处理器系统和计算机程序产品。

公开(公告)号：US08966286B2

公开(公告)日：2015-02-24

申请号：US13133958

申请日：2009-01-05

申请人： Alistair Robertson ,  Derek Beattie ,  James Andrew Collier Scobie

发明人： Alistair Robertson ,  Derek Beattie ,  James Andrew Collier Scobie

IPC分类号： G06F11/30 ,  G06F21/31 ,  G06F21/79

CPC分类号： G06F21/31 ,  G06F21/79

摘要： A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

摘要翻译： 系统包括可操作地耦合到至少一个存储器元件的信号处理逻辑，并且被布置为使得能够访问所述至少一个存储器元件。 所述信号处理逻辑被配置为接收安全密钥，使用所接收的安全密钥和系统特定的种子来生成系统密钥，将生成的系统密钥与存储在所述至少一个存储器的存储区域中的参考密钥进行比较 记忆元素 信号处理逻辑还被布置为至少部分地基于所生成的系统密钥与存储在存储器中的参考密钥的比较来配置对至少一个存储器元件的访问级别。

公开(公告)号：US20120131241A1

公开(公告)日：2012-05-24

申请号：US13384835

申请日：2009-07-20

申请人： Alistair Robertson ,  Joseph Circello ,  Mark Maiolani

发明人： Alistair Robertson ,  Joseph Circello ,  Mark Maiolani

IPC分类号： G06F5/00

CPC分类号： G06F12/0862 ,  G06F9/3804 ,  G06F9/3814 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/6022

摘要： A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

摘要翻译： 一种信号处理系统，包括缓冲器控制逻辑，其被布置为分配用于存储从至少一个存储器元件获得的信息的多个缓冲器。 在接收到要缓冲的取得的信息时，缓冲器控制逻辑被设置为根据以下中的至少一个来对要缓冲的信息进行分类：与顺序流相关联的第一类别和与流动变化相关联的第二类别，并且优先分别 当分配用于存储要获取的要缓冲的信息的缓冲器时，来自多个缓冲器的缓冲器存储与缓冲器相关联的与顺序流相关的第一类别的信息，所述缓冲器存储与关于流动变化相关联的第二类别的信息。

公开(公告)号：US20120124336A1

公开(公告)日：2012-05-17

申请号：US13382796

申请日：2009-07-20

申请人： Alistair Robertson ,  Joseph Circello ,  Mark Maiolani

发明人： Alistair Robertson ,  Joseph Circello ,  Mark Maiolani

IPC分类号： G06F9/30

CPC分类号： G06F13/1631 ,  G06F12/0862

摘要： A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a memory access request from the at least one master device, the prefetch module is arranged to configure the enabling of prefetching of at least one of instruction information and data information in relation to that memory access request based at least partly on an address to which the memory access request relates.

摘要翻译： 一种信号处理系统，包括至少一个主设备，至少一个存储器元件和预取模块，被配置为当从所述至少一个主设备到所述至少一个存储器元件的存储器访问请求时，从至少一个存储器元件执行预取。 在从至少一个主设备接收到存储器访问请求之后，预取模块被配置为至少部分地基于一个地址来配置使得能够相对于该存储器访问请求预取指令信息和数据信息中的至少一个 存储器访问请求涉及哪个。

公开(公告)号：US06376688B1

公开(公告)日：2002-04-23

申请号：US08817430

申请日：1997-05-29

申请人： Antonio Ferrante ,  Alfred Poulos ,  Christopher John Easton ,  Michael Joseph Pitt ,  Thomas Alistair Robertson ,  Deborah Ann Rathjen

发明人： Antonio Ferrante ,  Alfred Poulos ,  Christopher John Easton ,  Michael Joseph Pitt ,  Thomas Alistair Robertson ,  Deborah Ann Rathjen

IPC分类号： C07B4500

CPC分类号： C07C409/04 ,  C07C59/60 ,  C07C69/708 ,  C07C323/52 ,  C07C409/16 ,  C07C409/40 ,  C07C409/42

摘要： The present invention provides polyunsaturated fatty acid compounds having antimalarial and/or neutrophil stimulatory activity. The polyunsaturated fatty acids contain 18-25 carbons and 1-6 double bonds and are characterized in that they have one or two substitutions selected from the group consisting of &bgr; oxa, &ggr; oxa, &bgr; thia and &ggr; thia. It is also preferred that the polyunsaturated fatty acid compound includes a further substitution selected from the group consisting of hydroxy, hydroperoxy, peroxy, carboxymethyl substitutions or attached to an amino acid. The invention also provides a method of producing an unsaturated oxa substituted fatty acid comprising reacting an unsaturated fatty acid alcohol with a carbene that is inserted in the OH bond of the alcohol, the invention further provides a method of treating inflammation with a composition comprising at least one hydroxy, hydroperoxy or peroxy derivative of a polyunsaturated fatty acid having a C18-24 carbon chain and 1-6 cis or trans double bonds.

摘要翻译： 本发明提供具有抗疟和/或中性粒细胞刺激活性的多不饱和脂肪酸化合物。 多不饱和脂肪酸含有18-25个碳原子和1-6个双键，其特征在于它们具有一个或两个选自β-氧杂，γ-氧杂，β-硫和γ-硫的取代基。 还优选多不饱和脂肪酸化合物包括选自羟基，氢过氧基，过氧基，羧甲基取代或连接于氨基酸的另外的取代基。 本发明还提供一种生产不饱和氧杂取代脂肪酸的方法，其包括使不饱和脂肪酸醇与插入醇的OH键中的卡宾反应，本发明还提供一种用至少包含至少 具有C18-24碳链和1-6个顺式或反式双键的多不饱和脂肪酸的一种羟基，氢过氧基或过氧化物衍生物。

公开(公告)号：US09135157B2

公开(公告)日：2015-09-15

申请号：US13988366

申请日：2010-11-22

申请人： Alistair Robertson ,  Mark Maiolani

发明人： Alistair Robertson ,  Mark Maiolani

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0215 ,  G06F9/3802 ,  G06F9/3816 ,  G06F12/0246 ,  G06F12/0862 ,  G06F2212/17 ,  G06F2212/2022 ,  G06F2212/6022

摘要： An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element.

摘要翻译： 一种集成电路装置，包括至少一个用于从至少一个存储元件预取数据线的预取模块。 预取模块被配置为确定所请求的数据块在所述至少一个存储器元件的相应数据行内的位置，至少部分地基于所确定的所述至少一个存储器元件的位置，确定要预取的后续数据行的数量 在所述至少一个存储器元件的相应数据线内请求的数据块，并且使来自所述至少一个存储器元件的n个连续数据行的预取。

公开(公告)号：US09118179B2

公开(公告)日：2015-08-25

申请号：US13880193

申请日：2010-11-22

申请人： Alistair Robertson ,  Carl Culshaw ,  Alan Devine

发明人： Alistair Robertson ,  Carl Culshaw ,  Alan Devine

IPC分类号： H02H3/20 ,  G01R19/00 ,  H03M1/12 ,  G01R19/165

CPC分类号： H02H3/20 ,  G01R19/0084 ,  G01R19/165 ,  H03M1/12 ,  H03M1/129

摘要： An integrated circuit device comprising at least one analog to digital converter. The at least one ADC comprises at least one input operably coupled to at least one external contact of the integrated circuit device. The integrated circuit device further comprises detection circuitry comprising at least one detection module. The at least one detection module being arranged to receive at a first input thereof an indication of a voltage level at the at least one input of the at least one ADC, compare the received indication to a threshold value, and if the received indication exceeds the threshold value, output an indication that an excessive voltage state at the at least one input of the at least one ADC has been detected.

摘要翻译： 一种包括至少一个模数转换器的集成电路装置。 至少一个ADC包括可操作地耦合到集成电路器件的至少一个外部触点的至少一个输入。 集成电路装置还包括检测电路，其包括至少一个检测模块。 所述至少一个检测模块被布置为在其第一输入处接收所述至少一个ADC的至少一个输入端的电压电平的指示，将所接收的指示与阈值进行比较，并且如果所接收的指示超过 输出在至少一个ADC的至少一个输入处已经检测到过电压状态的指示。

公开(公告)号：US20150169494A1

公开(公告)日：2015-06-18

申请号：US14409314

申请日：2012-07-03

申请人： Alistair Robertson ,  Manfred Thanner

发明人： Alistair Robertson ,  Manfred Thanner

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F9/445

CPC分类号： G06F13/4221 ,  G06F1/3203 ,  G06F1/3243 ,  G06F9/44505 ,  G06F13/4022 ,  Y02D10/152

摘要： A data path configuration component for configuring at least one data path setting within a signal processing device is described. The data path configuration component is arranged to receive an indication of an operating mode of the signal processing device, and dynamically configure the at least one data path setting within the signal processing device based at least partially on the received indication of an operating mode of the signal processing device.

摘要翻译： 描述用于配置信号处理设备内的至少一个数据路径设置的数据路径配置组件。 数据路径配置组件被布置成接收信号处理设备的操作模式的指示，并且至少部分地基于接收到的信号处理设备的操作模式的指示来动态地配置信号处理设备内的至少一个数据路径设置 信号处理装置。

公开(公告)号：US20130232330A1

公开(公告)日：2013-09-05

申请号：US13988425

申请日：2010-11-22

申请人： Mark Maiolani ,  Alistair Robertson

发明人： Mark Maiolani ,  Alistair Robertson

IPC分类号： G06F9/44

CPC分类号： G06F9/4401 ,  F02D41/064 ,  F02D41/2432 ,  F02D41/2487 ,  F02D41/266 ,  G06F9/4403

摘要： A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialisation data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialisation data.

摘要翻译： 提供了一种用于在微控制器单元设备启动期间进行校准的方法。 该方法包括在MCU设备内，从可操作地耦合到MCU设备的外部支持设备中的至少一个存储器元件读取覆盖初始化数据，以及配置MCU设备的存储器映射功能以覆盖存储在至少一部分 具有存储在外部支持设备的至少一个存储器元件内的校准数据的MCU器件的器件存储器，根据覆盖初始化数据。