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    BIOSYNTHESIS OF PRODUCTS FROM 1-CARBON COMPOUNDS
    2.
    发明申请
    BIOSYNTHESIS OF PRODUCTS FROM 1-CARBON COMPOUNDS 审中-公开

    公开(公告)号：US20190100741A1

    公开(公告)日：2019-04-04

    申请号：US15523284

    申请日：2015-10-29

    申请人： Ramon GONZALEZ ,  Alexander CHOU ,  James CLOMBURG

    发明人： Ramon GONZALEZ ,  Alexander CHOU ,  James CLOMBURG

    IPC分类号： C12N9/88 ,  C12N15/52 ,  C12N15/70 ,  C12P7/20

    摘要： An engineered microbe that contains a designed platform for the conversion of one-carbon substrates to chemical products is described. The designed platform embodies a new metabolic architecture that consolidates carbon fixation, central metabolism, and product synthesis into a single pathway. This is made possible by the key finding that 2-hydroxyacyl-CoA lyase, an enzyme in the α-oxidation pathway, is capable of catalyzing the C—C bond formation between formyl-CoA and aldehydes of different chain lengths, allowing for the elongation of the carbon backbone of said aldehyde by one-carbon units. These novel microbes present an opportunity for the production of chemicals from single-carbon feedstocks such as carbon dioxide, carbon monoxide, formate, formaldehyde, methanol or methane.

    Methods for determining on-chip interconnect process parameters
    3.
    发明授权
    Methods for determining on-chip interconnect process parameters 有权
    确定片上互连工艺参数的方法

    公开(公告)号：US06291254B1

    公开(公告)日：2001-09-18

    申请号：US09244616

    申请日：1999-02-04

    申请人： Shih-tsun Alexander Chou ,  Keh-Jeng Chang ,  Robert G. Mathews

    发明人： Shih-tsun Alexander Chou ,  Keh-Jeng Chang ,  Robert G. Mathews

    IPC分类号： G01L2166

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

    摘要翻译： 一种方法提供了用于制造集成电路的过程中物理互连过程参数值的估计。 该方法包括制造测试结构，每个测试结构提供与物理互连过程参数的值的范围内的值相对应的可测量的值。 在一些实施例中，测量值用于通过使用场求解器的数值方法或通过闭式解决方案来导出物理互连过程参数的值。 涉及物理尺寸的物理互连工艺参数的值也可以通过测量使用扫描电子显微镜从测试结构的横截面获得的显微照片来获得。 在一些实施例中，测量对应于导体宽度的范围和导体之间的间隔范围的一系列测试结构。

    Methods for determining on-chip interconnect process parameters
    4.
    发明授权
    Methods for determining on-chip interconnect process parameters 失效
    确定片上互连工艺参数的方法

    公开(公告)号：US6057171A

    公开(公告)日：2000-05-02

    申请号：US937393

    申请日：1997-09-25

    申请人： Shih-tsun Alexander Chou ,  Keh-Jeng Chang ,  Robert G. Mathews

    发明人： Shih-tsun Alexander Chou ,  Keh-Jeng Chang ,  Robert G. Mathews

    IPC分类号： H01L23/544 ,  H01L21/66 ,  G01R31/26

    CPC分类号： H01L22/34 ,  H01L2924/0002

    摘要： A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

    摘要翻译： 一种方法提供了用于制造集成电路的过程中物理互连过程参数值的估计。 该方法包括制造测试结构，每个测试结构提供与物理互连过程参数的值的范围内的值相对应的可测量的值。 在一些实施例中，测量值用于通过使用场求解器的数值方法或通过闭式解决方案来导出物理互连过程参数的值。 涉及物理尺寸的物理互连工艺参数的值也可以通过测量使用扫描电子显微镜从测试结构的横截面获得的显微照片来获得。 在一些实施例中，测量对应于导体宽度的范围和导体之间的间隔范围的一系列测试结构。

    Methods for determining on-chip interconnect process parameters
    8.
    发明授权
    Methods for determining on-chip interconnect process parameters 有权

    公开(公告)号：US06312963B1

    公开(公告)日：2001-11-06

    申请号：US09245812

    申请日：1999-02-04

    申请人： Shih-Tsun Alexander Chou ,  Keh-Jeng Chang ,  Robert G. Mathews

    发明人： Shih-Tsun Alexander Chou ,  Keh-Jeng Chang ,  Robert G. Mathews

    IPC分类号： G01L2166

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.