公开(公告)号：US20100055871A1

公开(公告)日：2010-03-04

申请号：US12615961

申请日：2009-11-10

申请人： Hussein I. Hanafi ,  Leonard Forbes ,  Alan R. Reinberg

发明人： Hussein I. Hanafi ,  Leonard Forbes ,  Alan R. Reinberg

IPC分类号： H01L21/28 ,  H01L21/30

CPC分类号： G11C16/0408 ,  H01L21/28273 ,  H01L27/11803 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.

摘要翻译： 提供了逻辑单元中存储器的方法，设备和系统。 一个或多个实施例包括使用具有第一栅极，第二栅极和第三栅极（例如，控制栅极，背栅极和浮置栅极）的单元结构作为逻辑单元中的存储器。 该方法包括将浮动栅极编程为第一状态以使逻辑单元中的存储器作为第一逻辑门类型工作。 该方法还包括将浮动栅极编程到第二状态以使逻辑单元中的存储器作为第二逻辑门类型工作。

公开(公告)号：US20080316828A1

公开(公告)日：2008-12-25

申请号：US11821462

申请日：2007-06-21

申请人： Hussein I. Hanafi ,  Leonard Forbes ,  Alan R. Reinberg

发明人： Hussein I. Hanafi ,  Leonard Forbes ,  Alan R. Reinberg

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： G11C16/0408 ,  H01L21/28273 ,  H01L27/11803 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.

摘要翻译： 提供了逻辑单元中存储器的方法，设备和系统。 一个或多个实施例包括使用具有第一栅极，第二栅极和第三栅极（例如，控制栅极，背栅极和浮置栅极）的单元结构作为逻辑单元中的存储器。 该方法包括将浮动栅极编程为第一状态以使逻辑单元中的存储器作为第一逻辑门类型工作。 该方法还包括将浮动栅极编程到第二状态以使逻辑单元中的存储器作为第二逻辑门类型工作。

公开(公告)号：US07453082B2

公开(公告)日：2008-11-18

申请号：US11494052

申请日：2006-07-27

申请人： Alan R. Reinberg ,  Renee Zahorik, legal representative

发明人： Russell C. Zahorik

IPC分类号： H01J47/00

CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

摘要： A memory cell and a method of fabricating the memory cell having a small active area are provided. By forming a spacer in a window that is sized at the photolithographic limit, in one embodiment, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.

摘要翻译： 提供了存储单元和制造具有小的有效面积的存储单元的方法。 通过在尺寸为光刻极限的窗口中形成间隔物，在一个实施例中，可以在小于光刻极限的电介质层中形成孔。 将电极材料沉积到孔中，并且将一层结构改变材料（例如硫族化物）沉积在下电极上，从而产生具有非常小且可再现的有效面积的存储元件。

公开(公告)号：US07217606B2

公开(公告)日：2007-05-15

申请号：US10222997

申请日：2002-08-19

申请人： Leonard Forbes ,  Wendell P. Noble ,  Alan R. Reinberg

发明人： Leonard Forbes ,  Wendell P. Noble ,  Alan R. Reinberg

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/8236

CPC分类号： H01L29/78648 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78639 ,  H01L29/78642

摘要： A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

摘要翻译： 一种用于形成NMOS和PMOS晶体管的方法，其包括沿着较高阶取向切割衬底并在其垂直表面上制造深亚微米级的NMOS和PMOS晶体管。 互补的NMOS和PMOS晶体管形成CMOS晶体管对。 晶体管优选地用于诸如存储器电路（例如DRAM）的结构中，这些DRAM又在基于处理器的系统中使用。 理想地，深亚微米NMOS和PMOS晶体管以速度饱和运行，以实现最佳切换操作。

公开(公告)号：US06946357B2

公开(公告)日：2005-09-20

申请号：US09945397

申请日：2001-08-30

申请人： Gurtej Singh Sandhu ,  Alan R. Reinberg

发明人： Gurtej Singh Sandhu ,  Alan R. Reinberg

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/90 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91 ,  Y10S257/906

摘要： Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

摘要翻译： 用于集成电路的集装箱结构及其制造方法。 容器结构在导电容器的顶部上具有电介质盖，以通过隔离导电碎片穿过相邻容器结构顶部的桥接来降低容器与容器短路的风险。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US06933207B2

公开(公告)日：2005-08-23

申请号：US10829213

申请日：2004-04-22

申请人： Luan Tran ,  Alan R. Reinberg

发明人： Luan Tran ,  Alan R. Reinberg

IPC分类号： H01L27/108 ,  H01L21/76 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/10805 ,  H01L21/765 ,  Y10S438/942

摘要： Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual memory cells is ideally equal less than 8F2, where “F” is no greater than 0.25 micron and is defined as equal to one-half of minimum pitch, with minimum pitch being defined as equal to the smallest distance of a line width plus width of a space immediately adjacent said line on one side of said line between said line and a next adjacent line in a repeated pattern within the array. The respective area is preferably no greater than about 7F2, and most preferably no greater than about 6F2.

摘要翻译： 存储器集成电路包括形成在半导体衬底上并占据其面积的存储器单元的阵列，阵列的至少一些存储器单元形成在半导体衬底内形成的有源区域的线中，该有源区域在相邻存储器单元之间是连续的，所述相邻存储器 通过形成在所述相邻存储单元之间的所述连续有效区域上的导线，相对于其间形成的连续有源区域彼此隔离。 阵列内的连续有效区域的至少一些相邻线路之间形成的LOCOS场氧化物彼此隔离。 单个存储单元消耗的相应面积理想地等于小于8F 2，其中“F”不大于0.25微米，并且被定义为等于最小间距的一半，最小间距为 定义为等于阵列中重复图案中所述线和下一相邻线之间的线宽加上与所述线的一侧上的所述直线相邻的空间的最小距离。 相应面积优选不大于约7°F 2，最优选不大于约6°F 2。

公开(公告)号：US06897540B1

公开(公告)日：2005-05-24

申请号：US09561794

申请日：2000-05-01

申请人： Alan R. Reinberg

发明人： Alan R. Reinberg

IPC分类号： H01L21/768 ,  H01L29/00 ,  H01L23/58 ,  H01L29/47 ,  H01L31/07 ,  H01L31/108 ,  H01L29/95

CPC分类号： H01L21/76865 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76841

摘要： A microelectronic device fabricating method includes providing a substrate having a beveled portion and forming a layer of structural material on the beveled portion. Some of the structural material can be removed from the beveled portion by anisotropic etching to form a device feature from the structural material. The device feature can be formed on the beveled portion as with a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Structural material can be removed from the beveled portion to form an edge defined feature on a substantially perpendicular edge of the substrate. The beveled portion and perpendicular edge can be part of a mandril. The mandril can be removed from the substrate after forming the edge defined feature.

摘要翻译： 微电子器件制造方法包括提供具有斜面部分并在斜面部分上形成结构材料层的衬底。 一些结构材料可以通过各向异性蚀刻从斜面部分去除以从结构材料形成装置特征。 装置特征可以形成在斜切部分上，如同一对间隔开的邻近的阻挡材料线，其基本上没有在其间延伸的剩余短路桁条。 结构材料可以从斜面部分移除，以在衬底的基本上垂直的边缘上形成边缘限定的特征。 倾斜部分和垂直边缘可以是曼角的一部分。 在形成边缘限定特征之后，可以将基板从基板上移除。

公开(公告)号：US06833579B2

公开(公告)日：2004-12-21

申请号：US09945497

申请日：2001-08-30

申请人： Gurtej Singh Sandhu ,  Alan R. Reinberg

发明人： Gurtej Singh Sandhu ,  Alan R. Reinberg

IPC分类号： H01L27108

CPC分类号： H01L28/90 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91 ,  Y10S257/906

摘要： Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

摘要翻译： 用于集成电路的集装箱结构及其制造方法。 容器结构在导电容器的顶部上具有电介质盖，以通过隔离导电碎片穿过相邻容器结构顶部的桥接来降低容器与容器短路的风险。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US06509626B2

公开(公告)日：2003-01-21

申请号：US09864559

申请日：2001-05-23

申请人： Alan R. Reinberg

发明人： Alan R. Reinberg

IPC分类号： H01L2906

CPC分类号： H01L25/167 ,  H01L21/28114 ,  H01L21/2815 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823468 ,  H01L33/486 ,  H01L2924/0002 ,  Y10S438/944 ,  Y10S438/978 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00

摘要： A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane. The substrate includes a first conductive device component of a first type which is elongated in a first direction generally parallel with the plane. A second conductive device component of the first type is included which is elongated in a second direction generally parallel with the plane, with the first and second conductive device components at least predominately comprise common conductive material. The first and second conductive device components have different base widths. At least one of the first and second conductive device components is elevationally angled from perpendicular to the plane along at least a majority of its elongated length in its respective first or second direction.

摘要翻译： 微电子器件制造方法包括提供具有沿着平面延伸的平均全局外表面的衬底。 第一部分形成在衬底上，包括直线部分，该平直线段从该平面成角度并且在该衬底上方形成第二部分，该第二部分包括直线段，该直线部分以与第一部分不同的角度从该平面倾斜。 在第一和第二部分上形成一层结构材料。 结构材料层被各向异性蚀刻，并且第一器件特征最终留在具有第一基底宽度的第一部分上，并且第二器件特征最终留在具有与第一基底宽度不同的第二基部宽度的第二部分上。 集成电路包括具有沿平面延伸的平均全局外表面的衬底。 衬底包括第一类型的第一导电器件部件，其在与该平面大致平行的第一方向上延伸。 包括第一类型的第二导电器件部件，其在大致平行于平面的第二方向上延伸，第一和第二导电器件部件至少主要包括公共导电材料。 第一和第二导电器件部件具有不同的基底宽度。 第一和第二导电器件部件中的至少一个在其相应的第一或第二方向上至少沿其细长长度的大部分从垂直于该平面垂直成角度。

公开(公告)号：US06492656B2

公开(公告)日：2002-12-10

申请号：US09815744

申请日：2001-03-23

申请人： Russell C. Zahorik ,  Alan R. Reinberg

发明人： Russell C. Zahorik ,  Alan R. Reinberg

IPC分类号： H01L4700

CPC分类号： H01L45/06 ,  H01L29/685 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

摘要： A method for fabricating chalcogenide memories in which ultra-small pores are formed in insulative layers using disposable spacers. The chalcogenide memory elements are positioned within the ultra-small pores. The chalcogenide memory elements thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms.

摘要翻译： 一种制造硫族化物存储器的方法，其中使用一次性间隔件在绝缘层中形成超小孔。 硫族化物记忆元件位于超小孔内。 如此限定的硫族化物记忆元件的最小横向尺寸范围为约500至4000埃。