公开(公告)号：US07941639B2

公开(公告)日：2011-05-10

申请号：US11481432

申请日：2006-07-05

申请人： Yannick Teglia ,  Pierre-Yvan Liardet ,  Alain Pomet

发明人： Yannick Teglia ,  Pierre-Yvan Liardet ,  Alain Pomet

IPC分类号： G06F9/30

CPC分类号： G06F21/77 ,  G06F11/0757 ,  G06F21/75 ,  G06Q20/341 ,  G07F7/082 ,  G07F7/084 ,  G07F7/1008

摘要： A method for protecting the execution of a main program against possible traps, including, on occurrence of an instruction from the main program, starting a time counter of a given count according to next instructions of the main program, and executing, once the counter has reached its count, at least one instruction of a secondary program from which the result of the main program depends.

摘要翻译： 一种用于保护主程序的执行免受可能的陷阱的方法，包括在发生来自主程序的指令时，根据主程序的下一个指令启动给定计数的时间计数器，一旦计数器具有 达到其计数，至少一个辅助程序的指令，主程序的结果从该程序所依赖。

公开(公告)号：US07881894B2

公开(公告)日：2011-02-01

申请号：US12089897

申请日：2006-06-10

申请人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

发明人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

摘要： One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i−1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i−1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i−1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

摘要翻译： 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号（0）到＆phgr;（2i-1）被提供有基本的时间步。 在接收的比特流中测量对应于比特持续时间的时间步长的合理数量。 将振荡器信号＆phgr（0）〜j（2i-1）变换成具有与所述时钟信号的有效边沿同步的时钟信号CK与至少一个振荡器信号（0）到（2i-1） 两个连续的有效边沿被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。

公开(公告)号：US07120813B2

公开(公告)日：2006-10-10

申请号：US10352749

申请日：2003-01-28

申请人： Robert Antoine Leydier ,  Christophe Alain Pomet

发明人： Robert Antoine Leydier ,  Christophe Alain Pomet

IPC分类号： H04L7/04 ,  G06F13/14

CPC分类号： G06F1/04

摘要： In one form of the invention, a method for generating a local clock signal responsive to signals on a Universal Serial Bus (“USB”) includes generating a frequency-bearing clock signal by a free running oscillator on an integrated circuitry chip of a device coupled to the USB. The oscillator runs at a frequency that is substantially stable but initially known with substantial inaccuracy. A single ended bit-serial signal is extracted from received signals sent by a USB host or hub and timing signals are responsively asserted. A bit pattern is detected in the single ended bit-serial signal and intervals are measured during which the timing signals are asserted. The period P of the local clock signal is adjusted responsive to one of the measured intervals. In one variant, the initial inaccuracy is at least partly because the oscillator consists solely of circuitry on the chip.

摘要翻译： 在本发明的一种形式中，响应于通用串行总线（“USB”）上的信号产生本地时钟信号的方法包括通过耦合的器件的集成电路芯片上的自由振荡器产生频率承载时钟信号 到USB。 振荡器以基本稳定的频率运行，但是最初以实质的不精确性已知。 从USB主机或集线器发送的接收信号中提取单端比特串行信号，响应地确定定时信号。 在单端比特串行信号中检测到位模式，并且在定时信号被断言期间测量间隔。 本地时钟信号的周期P响应于测量的间隔之一来调整。 在一个变型中，初始不准确性至少部分是因为振荡器仅由芯片上的电路组成。

公开(公告)号：US06362671B1

公开(公告)日：2002-03-26

申请号：US09771364

申请日：2001-01-26

申请人： Alexandre Malherbe ,  Fabrice Marinet ,  Alain Pomet

发明人： Alexandre Malherbe ,  Fabrice Marinet ,  Alain Pomet

IPC分类号： H03K501

摘要： A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

公开(公告)号：US08195946B2

公开(公告)日：2012-06-05

申请号：US11402307

申请日：2006-04-11

申请人： Fabrice Romain ,  Alain Pomet

发明人： Fabrice Romain ,  Alain Pomet

IPC分类号： H04L9/32 ,  G06F11/30

CPC分类号： G06F21/52 ,  G06F21/77 ,  G06F21/79 ,  H04L9/004

摘要： A method and a circuit for checking the coherence between data read from a first area of a memory of a microcontroller and the address of these data, including calculating a current digital signature of the read data by a function also taking into account the address of these data in the memory, and checking the coherence between the current signature and a previously-recorded signature.

摘要翻译： 一种用于检查从微控制器的存储器的第一区域读取的数据与这些数据的地址之间的相干性的方法和电路，包括通过功能计算读取数据的当前数字签名，同时考虑到这些数据的地址 存储器中的数据，以及检查当前签名与之前记录的签名之间的一致性。

公开(公告)号：US08135129B2

公开(公告)日：2012-03-13

申请号：US11917347

申请日：2006-06-14

申请人： Yannick Teglia ,  Pierre-Yvan Liardet ,  Alain Pomet

发明人： Yannick Teglia ,  Pierre-Yvan Liardet ,  Alain Pomet

IPC分类号： H04L9/28 ,  G06F12/14 ,  H04L9/32

CPC分类号： G06F7/723 ,  G06F2207/7252 ,  H04L9/003

摘要： A method and a circuit for protecting a numerical quantity contained in an integrated circuit on a first number of bits, in a modular exponentiation computing of a data by the numerical quantity, including: selecting at least one second number included between the unit and said first number minus two; dividing the numerical quantity into at least two parts, a first part including, from the bit of rank null, a number of bits equal to the second number, a second part including the remaining bits; for each part of the quantity, computing a first modular exponentiation of said data by the part concerned and a second modular exponentiation of the result of the first by the FIG. 2 exponentiated to the power of the rank of the first bit of the part concerned; and computing the product of the results of the first and second modular exponentiations.

摘要翻译： 一种方法和电路，用于通过所述数字量对数据的模幂运算中的第一位数保护包含在集成电路中的数值，包括：选择包括在所述单元和所述第一位之间的至少一个第二数字 数减二; 将所述数值分为至少两部分，第一部分包括从所述位零位的比特数等于所述第二数目的第二部分，包括剩余比特的第二部分; 对于数量的每个部分，通过所涉及的部分计算所述数据的第一模幂运算，并且通过图1计算第一次的结果的第二模幂运算。 2指数与有关部分的第一位的等级的权力; 并计算第一和第二模幂指数的结果的乘积。

公开(公告)号：US20100281197A1

公开(公告)日：2010-11-04

申请号：US12809898

申请日：2007-12-21

申请人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

发明人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4027

摘要： A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

摘要翻译： 桥电路10设置在第一数据端口A1，A2和第二数据端口B1，B2之间。 桥接电路包括第一收发器级40，其包括至少一个输入缓冲器11,14和与第一数据端口链接的至少一个三态输出缓冲器12,13;第二收发器级50，包括至少一个输入缓冲器21， 24和连接到第二数据端口的至少一个三态输出缓冲器12,13，用于检测第一数据端口到达分组的第一检测电路31，用于检测分组到达的第二检测电路37 由第二个数据端口。 选择电路34,35可以根据由第一和第二检测电路进行的检测来输出第一或第二收发器级的三态输出缓冲器。

公开(公告)号：US07593258B2

公开(公告)日：2009-09-22

申请号：US11641550

申请日：2006-12-19

申请人： Pierre-Yvan Liardet ,  Yannick Teglia ,  Alain Pomet

发明人： Pierre-Yvan Liardet ,  Yannick Teglia ,  Alain Pomet

IPC分类号： G11C11/34

CPC分类号： G06F21/75 ,  G06F21/755 ,  G06F21/77

摘要： A method for protecting an integrated circuit, including at least one non-volatile memory, including the steps of detecting a possible disturbance in the flow of a program executed by the integrated circuit, modifying the value of a digital variable in a volatile storage element in case of a disturbance detection and, in a way independent in time from the detection, intervening upon the non-volatile memory according to the value of said variable.

摘要翻译： 一种用于保护包括至少一个非易失性存储器的集成电路的方法，包括以下步骤：检测由集成电路执行的程序的流动中可能的干扰，修改易失性存储元件中的数字变量的值 干扰检测的情况，并且以与检测不同的时间独立的方式，根据所述变量的值插入在非易失性存储器上。

公开(公告)号：US20080231328A1

公开(公告)日：2008-09-25

申请号：US12089897

申请日：2006-06-10

申请人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

发明人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

IPC分类号： H03B21/00 ,  G06F1/04 ,  G06K19/067

CPC分类号： G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

摘要： One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

摘要翻译： 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号phi（0）到phi（2I i-1）被提供有基本的时间步骤。 在接收的比特流中测量对应于比特持续时间的时间步长的合理数量。 振荡器信号phi（0）至j（2-i-1）被转换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号phi（0）至phi （2 1>），两个连续的有效边沿被分开与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。