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    Instruction control apparatus for loading plurality of instructions into execution stage
    3.
    发明授权
    Instruction control apparatus for loading plurality of instructions into execution stage 有权
    用于将多个指令加载到执行阶段的指令控制装置

    公开(公告)号：US06530013B1

    公开(公告)日：2003-03-04

    申请号：US09461422

    申请日：1999-12-16

    申请人： Michiharu Hara ,  Aiichiro Inoue

    发明人： Michiharu Hara ,  Aiichiro Inoue

    IPC分类号： G06F9312

    CPC分类号： G06F9/3816 ,  G06F9/30149

    摘要： In an instruction control apparatus that enables a plurality of instructions of different instruction lengths to be selected simultaneously from an instruction buffer, the amount of circuitry is reduced while achieving high speed processing. The instruction control apparatus includes a selection circuit and a pointer that points to the beginning of the next instruction word, within the instruction sequence fetched in a holding means, to be loaded into an execution stage. The selection circuit first selects a portion of the instruction sequence, starting from the beginning pointed to by the pointer and extending until reaching a maximum length of instructions that can be loaded into the execution stage, then simultaneously examines the lengths of instructions contained in the selected portion on the basis of a minimum instruction length unit, and selects the plurality of instructions to be loaded into the execution stage, based on the combination of the instruction lengths. One or more instructions thus selected are held in a plurality of loading ports.

    摘要翻译： 在能够从指令缓冲器同时选择不同指令长度的多个指令的指令控制装置中，在实现高速处理的同时减少电路的数量。 指令控制装置包括选择电路和指向下一个指令字的起始位置的指针，该指针在保持装置中取出的指令序列中被加载到执行阶段。 选择电路首先从指针指向的开始首先选择指令序列的一部分，并延伸直到达到可以加载到执行阶段的指令的最大长度，然后同时检查包含在所选择的指令中的指令长度 并根据指令长度的组合选择要加载到执行阶段的多个指令。 如此选择的一个或多个指令被保存在多个加载端口中。

    Method and apparatus for controlling instruction in pipeline processor
    4.
    发明授权
    Method and apparatus for controlling instruction in pipeline processor 失效
    管道处理器控制指令的方法和装置

    公开(公告)号：US5642500A

    公开(公告)日：1997-06-24

    申请号：US303835

    申请日：1994-09-09

    申请人： Aiichiro Inoue

    发明人： Aiichiro Inoue

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3806

    摘要： A pipeline processor for processing instruction fetch prior to execution of the instruction based on the content of branch history for storing history of the result of execution of branch instructions includes an address generating section, branch history retrieving section, prefetch address holding section and instruction fetch section. The branch history retrieving section determines whether each of addresses sequentially generated from the address generating section hits the branch history or not. When an instruction stored in the address hits the branch history, the branch history retrieving section supplies the content of the branch history to the prefetch address holding section. When the branch history retrieving section is hit, the prefetch address holding section holds the branching-destination address of the branch instruction until the instruction is fetched by the instruction fetch section. If an instruction fetched in a preceding cycle hits the branch history, the instruction fetch section fetches an instruction of an address held in the prefetch address holding section, and if the instruction fetched in a preceding cycle does not hit the branch history, the instruction fetch section fetches an instruction of an address generated from the address generating section.

    摘要翻译： 一种用于在基于用于存储分支指令的执行结果的历史的分支历史的内容之前处理指令执行的流水线处理器包括地址生成部分，分支历史检索部分，预取地址保持部分和指令获取部分 。 分支历史检索部分确定从地址生成部分顺序生成的每个地址是否触及分支历史。 当存储在地址中的指令命中分支历史时，分支历史检索部分将分支历史的内容提供给预取地址保持部分。 当分支历史检索部分被命中时，预取地址保持部分保持分支指令的分支目的地地址，直到指令被指令获取部分取出。 如果在前一个循环中获取的指令命中分支历史，则指令获取部分取出保留在预取地址保存部分中的地址的指令，并且如果在前一周期中获取的指令未触发分支历史，则指令获取 部分获取从地址生成部分生成的地址的指令。

    Information processing device, memory control method, and memory control device
    6.
    发明申请
    Information processing device, memory control method, and memory control device 失效
    信息处理装置，存储器控制方法和存储器控制装置

    公开(公告)号：US20090240893A1

    公开(公告)日：2009-09-24

    申请号：US12330822

    申请日：2008-12-09

    申请人： Go Sugizaki ,  Aiichiro Inoue ,  Naozumi Aoki ,  Tsuyoshi Motokurumada

    发明人： Go Sugizaki ,  Aiichiro Inoue ,  Naozumi Aoki ,  Tsuyoshi Motokurumada

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822

    摘要： The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes each having a main memory and a processor including a cache memory, the system controller of at least one of the nodes is designed to include a holding unit that holds specific information about primary data present in the main memory of its subject node, with the cache data corresponding to the primary data not present in the cache memory of the nodes other than its subject node. With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved.

    摘要翻译： 本发明提供一种信息处理装置，存储器控制方法和存储器控制装置。 在包括各自具有主存储器的节点和包括高速缓存存储器的处理器的信息处理设备中，至少一个节点的系统控制器被设计为包括保持单元，该保持单元保存有关主存储器中存在的主数据的特定信息 的主体节点，其中高速缓存数据对应于不存在于除了其主节点之外的节点的高速缓冲存储器中的主数据。 利用这种结构，每个存储器访问的延迟被缩短，并且提高了每次窥探操作的吞吐量。

    Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof
    7.
    发明授权
    Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof 失效
    设备预测与子程序返回相当的指令的分支及其方法

    公开(公告)号：US06898698B1

    公开(公告)日：2005-05-24

    申请号：US09533042

    申请日：2000-03-22

    申请人： Ryuichi Sunayama ,  Masaki Ukai ,  Aiichiro Inoue

    发明人： Ryuichi Sunayama ,  Masaki Ukai ,  Aiichiro Inoue

    IPC分类号： G06F9/38 ,  G06F9/42 ,  G06F15/00

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3867

    摘要： A register number of a link register, which is specified by an instruction equivalent to a subroutine call, is registered. The number of a branch destination register in a branch instruction which can possibly be an instruction equivalent to a subroutine return is compared with the registered register number. If they match, this branch instruction is identified as an instruction equivalent to a subroutine return.

    摘要翻译： 注册由与子程序调用相当的指令指定的链接寄存器的寄存器编号。 将可能是与子程序返回相当的指令的分支指令中的分支目的地寄存器的数量与注册的寄存器编号进行比较。 如果它们匹配，则该分支指令被识别为等同于子程序返回的指令。

    Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions
    8.
    发明授权
    Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions 失效
    指令处理装置使用通过控制指令的早期加载来实现再读操作的微程序

    公开(公告)号：US06754814B1

    公开(公告)日：2004-06-22

    申请号：US09461424

    申请日：1999-12-16

    申请人： Hiroki Narita ,  Aiichiro Inoue

    发明人： Hiroki Narita ,  Aiichiro Inoue

    IPC分类号： G06F900

    CPC分类号： G06F9/24 ,  G06F9/30101 ,  G06F9/30145

    摘要： An instruction processing apparatus using a microprogram instruction which implements re-reading operation. The instruction execution apparatus is provided with a queue stack, a unit halting requests for reading subsequent instructions at the instruction of a microprogram, and a unit releasing this halt. Further, by instruction the reading of the subsequent instructions using the microprogram control information, it becomes possible to simultaneously execute the microprogram and instruction re-reading processing. Because the Program Status Word Instruction Address (PSWIAR) of the load control (LCTL) plus the instruction length of the PSWIAR makes an instruction fetch address of the LCTL, the hardware of the instruction re-read address production circuit (which is a part of the instruction processing circuit) can be used. This reduces the: T-cycle instruction address register (TIAR), T-cycle instruction length code (TILC), A-cycle instruction address register (AIAR), the A-cycle instruction length code (AILC), and an adder for adding the TILC with the TIAR.

    摘要翻译： 一种使用微程序指令进行再读操作的指令处理装置。 指令执行装置设置有队列堆栈，在微程序的指令中停止读取后续指令的请求单元，以及释放该暂停的单元。 此外，通过指令使用微程序控制信息读取后续指令，可以同时执行微程序和指令重新读取处理。 由于负载控制（LCTL）的程序状态字指令地址（PSWIAR）加上PSWIAR的指令长度使得LCTL的指令获取地址指令重新读取地址生成电路的硬件（它是 指令处理电路）。 这减少了：T周期指令地址寄存器（TIAR），T周期指令长度代码（TILC），A周期指令地址寄存器（AIAR），A周期指令长度代码（AILC）和加法器 TILC与TIAR。

    Instruction controlling system and method thereof
    9.
    发明授权
    Instruction controlling system and method thereof 失效
    指令控制系统及其方法

    公开(公告)号：US6016541A

    公开(公告)日：2000-01-18

    申请号：US42797

    申请日：1998-03-17

    申请人： Kyoko Tashima ,  Takeo Asakawa ,  Aiichiro Inoue

    发明人： Kyoko Tashima ,  Takeo Asakawa ,  Aiichiro Inoue

    IPC分类号： G06F9/38 ,  G06F15/00

    CPC分类号： G06F9/384 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857

    摘要： A general-purpose register address output from an instruction register is read and changed to a corresponding register update buffer address in an update table. Additionally, the update reservation instructing bit corresponding to the general-purpose register address is read out from a register update reservation table. If its value is "0", the general-purpose register address is provided to the general-purpose register, and the data stored at that address is input to an arithmetic unit. If the value of the bit is "1", the contents of the corresponding entry in the update table is registered to a reservation station. The reservation station determines the execution order of respective entries, and sequentially provides a register update buffer address to a register update buffer, and inputs the data stored at that address to the arithmetic unit.

    摘要翻译： 读取从指令寄存器输出的通用寄存器地址，并将其更改为更新表中相应的寄存器更新缓冲区地址。 此外，从寄存器更新预约表读出对应于通用寄存器地址的更新预约指令位。 如果其值为“0”，则将通用寄存器地址提供给通用寄存器，并将存储在该地址处的数据输入到运算单元。 如果该位的值为“1”，则将更新表中的相应条目的内容登记到保留站。 保留站确定各个条目的执行顺序，并且向寄存器更新缓冲器顺序提供寄存器更新缓冲器地址，并将存储在该地址的数据输入到运算单元。

    Virtual storage address space access control system including auxiliary translation lookaside buffer
    10.
    发明授权
    Virtual storage address space access control system including auxiliary translation lookaside buffer 失效
    虚拟存储地址空间访问控制系统，包括辅助翻译后备缓冲区

    公开(公告)号：US5923864A

    公开(公告)日：1999-07-13

    申请号：US557707

    申请日：1990-07-25

    申请人： Aiichiro Inoue

    发明人： Aiichiro Inoue

    IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/1036

    摘要： A virtual storage address space access control system has an access register having a plurality of access register numbers, a dynamic address translation unit and translation lookaside buffer for translating a virtual address to a real address by using a segment table designation. It further comprises first and second control registers for designating primary and secondary spaces, respectively, the primary and secondary spaces being accessed when the content of the access register is "1" or "0". Also included are access register translation lookaside buffer for indirectly obtaining a segment table designation by using a content of the access register and access register auxiliary translation lookaside buffer for directly obtaining the segment table designation by using the access register number.

    摘要翻译： 虚拟存储地址空间访问控制系统具有具有多个访问寄存器编号的访问寄存器，用于通过使用段表指定将虚拟地址转换为实地址的动态地址转换单元和翻译后备缓冲器。 它还包括第一和第二控制寄存器，分别用于指定主空间和辅助空间，当访问寄存器的内容为“1”或“0”时，被访问的主空间和辅助空间。 还包括访问寄存器翻译后备缓冲器，用于通过使用访问寄存器和访问寄存器辅助翻译后备缓冲器的内容来间接获得段表指定，以便通过使用访问寄存器号直接获取段表指定。