公开(公告)号：US07765387B2

公开(公告)日：2010-07-27

申请号：US10352005

申请日：2003-01-28

Applicant: Ryuichi Sunayama ,  Kuniki Morita ,  Aiichiro Inoue

Inventor： Ryuichi Sunayama ,  Kuniki Morita ,  Aiichiro Inoue

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC classification number: G06F9/321 ,  G06F9/3842 ,  G06F9/3844

Abstract: A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.

Abstract translation: 程序计数器控制方法通过使用分支预测机制的无序方法来控制指令，并且控制具有用于分支的延迟指令的架构。 该方法包括以下步骤：当分支预测成功并且分支指令分支时同时提交包括分支指令的多个指令，并且根据所提交的指令的数目同时更新程序计数器和下一个程序计数器。

公开(公告)号：US06530013B1

公开(公告)日：2003-03-04

申请号：US09461422

申请日：1999-12-16

Applicant: Michiharu Hara ,  Aiichiro Inoue

Inventor： Michiharu Hara ,  Aiichiro Inoue

IPC: G06F9312

CPC classification number: G06F9/3816 ,  G06F9/30149

Abstract: In an instruction control apparatus that enables a plurality of instructions of different instruction lengths to be selected simultaneously from an instruction buffer, the amount of circuitry is reduced while achieving high speed processing. The instruction control apparatus includes a selection circuit and a pointer that points to the beginning of the next instruction word, within the instruction sequence fetched in a holding means, to be loaded into an execution stage. The selection circuit first selects a portion of the instruction sequence, starting from the beginning pointed to by the pointer and extending until reaching a maximum length of instructions that can be loaded into the execution stage, then simultaneously examines the lengths of instructions contained in the selected portion on the basis of a minimum instruction length unit, and selects the plurality of instructions to be loaded into the execution stage, based on the combination of the instruction lengths. One or more instructions thus selected are held in a plurality of loading ports.

Abstract translation: 在能够从指令缓冲器同时选择不同指令长度的多个指令的指令控制装置中，在实现高速处理的同时减少电路的数量。 指令控制装置包括选择电路和指向下一个指令字的起始位置的指针，该指针在保持装置中取出的指令序列中被加载到执行阶段。 选择电路首先从指针指向的开始首先选择指令序列的一部分，并延伸直到达到可以加载到执行阶段的指令的最大长度，然后同时检查包含在所选择的指令中的指令长度 并根据指令长度的组合选择要加载到执行阶段的多个指令。 如此选择的一个或多个指令被保存在多个加载端口中。

公开(公告)号：US5642500A

公开(公告)日：1997-06-24

申请号：US303835

申请日：1994-09-09

Applicant: Aiichiro Inoue

Inventor： Aiichiro Inoue

IPC: G06F9/38

CPC classification number: G06F9/3806

Abstract: A pipeline processor for processing instruction fetch prior to execution of the instruction based on the content of branch history for storing history of the result of execution of branch instructions includes an address generating section, branch history retrieving section, prefetch address holding section and instruction fetch section. The branch history retrieving section determines whether each of addresses sequentially generated from the address generating section hits the branch history or not. When an instruction stored in the address hits the branch history, the branch history retrieving section supplies the content of the branch history to the prefetch address holding section. When the branch history retrieving section is hit, the prefetch address holding section holds the branching-destination address of the branch instruction until the instruction is fetched by the instruction fetch section. If an instruction fetched in a preceding cycle hits the branch history, the instruction fetch section fetches an instruction of an address held in the prefetch address holding section, and if the instruction fetched in a preceding cycle does not hit the branch history, the instruction fetch section fetches an instruction of an address generated from the address generating section.

Abstract translation: 一种用于在基于用于存储分支指令的执行结果的历史的分支历史的内容之前处理指令执行的流水线处理器包括地址生成部分，分支历史检索部分，预取地址保持部分和指令获取部分 。 分支历史检索部分确定从地址生成部分顺序生成的每个地址是否触及分支历史。 当存储在地址中的指令命中分支历史时，分支历史检索部分将分支历史的内容提供给预取地址保持部分。 当分支历史检索部分被命中时，预取地址保持部分保持分支指令的分支目的地地址，直到指令被指令获取部分取出。 如果在前一个循环中获取的指令命中分支历史，则指令获取部分取出保留在预取地址保存部分中的地址的指令，并且如果在前一周期中获取的指令未触发分支历史，则指令获取 部分获取从地址生成部分生成的地址的指令。

公开(公告)号：US06993638B2

公开(公告)日：2006-01-31

申请号：US10163573

申请日：2002-06-07

Applicant: Masaki Ukai ,  Aiichiro Inoue

Inventor： Masaki Ukai ,  Aiichiro Inoue

IPC: G06F12/00

CPC classification number: G06F9/355 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0862 ,  G06F12/1054

Abstract: If a base register value, an index register value and a displacement value are given in the case of operand access, these values are inputted to an arithmetic unit to generate a correctly calculated logical address. Simultaneously, a logical address predicting unit predicts a logical address. An absolute address is predicted based on the predicted logical address by using an absolute address history table. Access to a cache memory (LBS) based on an absolute address is made using the predicted absolute address to obtain cache data. Then, the arithmetic unit calculates a correct absolute address using the correctly calculated address using a TLB and checks if the correct absolute address coincides with the predicted absolute address so as to perform result confirmation of the cache data read from the LBS. In the case of instruction fetch, similar processing is carried out except that the calculation of a logical address is not performed.

公开(公告)号：US06851043B1

公开(公告)日：2005-02-01

申请号：US09461297

申请日：1999-12-15

Applicant: Aiichiro Inoue

Inventor： Aiichiro Inoue

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3885

Abstract: An information processing device contains a branch instruction execution control apparatus including a branch reservation station unit as a stack waiting for a process. The branch reservation station unit generates an entry storing a branch or data required to process the branch if an instruction is decoded, and it is determined that the instruction is a branch instruction or a process is required for a branch. With the configuration, in the information processing device for executing sequentially given instructions, a process of a sequence of instructions containing a branch instruction can be performed at a high speed to process the branch instruction in an order different from an order specified by a program.

Abstract translation: 信息处理装置包括分支指令执行控制装置，其包括作为等待处理的堆栈的分支预留站单元。 如果指令被解码，则分支保留站单元生成存储分支或处理分支所需的数据的条目，并且确定指令是分支指令或分支需要处理。 利用该配置，在用于执行顺序给出的指令的信息处理装置中，可以高速执行包含转移指令的指令序列的处理，以与程序指定的顺序不同的顺序处理分支指令。

公开(公告)号：US06532534B1

公开(公告)日：2003-03-11

申请号：US09456918

申请日：1999-12-07

Applicant: Ryuichi Sunayama ,  Aiichiro Inoue

Inventor： Ryuichi Sunayama ,  Aiichiro Inoue

IPC: G06F938

CPC classification number: G06F9/3806 ,  G06F9/3844

Abstract: The present invention relates to an information processing apparatus provided with a branch history. An object of the present invention is to automatically designate a way in which an entry to be data-processed exists among a plurality of ways with which the branch history is provided, and is to speed up the process. In order to accomplish this objective, the present invention comprises an instruction fetch unit attaching way designation information designating a way in which the entry to be data-processed exists to the address of an instruction, and provides the information to an instruction execution unit in preparation for the case where the instruction fetched from a storage unit is a branch instruction and the data process of a branch history corresponding to the branch instruction is required.

Abstract translation: 本发明涉及具有分支历史的信息处理装置。 本发明的目的是自动指定在提供分支历史的多种方式之间存在要进行数据处理的条目的方式，并且加速处理。 为了实现该目的，本发明包括指令获取单元附加方式指定信息，其指定要将数据处理的条目存在于指令的地址的方式，并且将信息提供给指令执行单元，以准备 对于从存储单元取出的指令是分支指令并且需要与分支指令相对应的分支历史的数据处理的情况。

公开(公告)号：US06502186B2

公开(公告)日：2002-12-31

申请号：US09739800

申请日：2000-12-20

Applicant: Aiichiro Inoue

Inventor： Aiichiro Inoue

IPC: G06F946

CPC classification number: G06F9/3836 ,  G06F9/384 ,  G06F9/3857

Abstract: An apparatus stores data corresponding to each type of instruction for each instruction, and includes: an information reservation station unit for performing integral control containing a resource updating process performed when the instruction is completely executed; and one or more function reservation station units for storing data corresponding to the function relating to the execution of the instruction, and controlling the execution of the function under the integral control of the instruction reservation station unit.

Abstract translation: 一种装置存储与各种指令对应的数据，包括：信息预约站单元，用于执行包含完全执行指令时执行的资源更新处理的整体控制; 以及一个或多个功能保留站单元，用于存储对应于与指令的执行有关的功能的数据，以及控制在指令预约站单元的积分控制下的功能的执行。

公开(公告)号：US06421771B1

公开(公告)日：2002-07-16

申请号：US09268998

申请日：1999-03-16

Applicant: Aiichiro Inoue

Inventor： Aiichiro Inoue

IPC: G06F938

CPC classification number: G06F9/383 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3834

Abstract: A register interference state where a register which is updated by a preceding instruction is used by a succeeding instruction, for example, for the generation of an operand address, is detected. When a register interference state is detected, the execution of a succeedingly fetched instruction is started by storing an operand address generated when the succeeding instruction is executed in association with the address of the succeeding instruction. The operand address is estimated which corresponds to the address of the succeedingly fetched instruction and is retrieved from the stored contents.

Abstract translation: 检测由例如用于产生操作数地址的后续指令使用由前一条指令更新的寄存器的寄存器干扰状态。 当检测到寄存器干扰状态时，通过存储与后续指令的地址相关联地执行后续指令生成的操作数地址来开始执行后续取出的指令。 估计操作数地址，其对应于随后取出的指令的地址，并从存储的内容中检索。

公开(公告)号：US5297267A

公开(公告)日：1994-03-22

申请号：US420780

申请日：1989-10-12

Applicant: Aiichiro Inoue

Inventor： Aiichiro Inoue

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F15/16 ,  G06F15/177 ,  G06F13/00 ,  G06F13/16

CPC classification number: G06F9/52

Abstract: A system and method for controlling a "serialization" of accesses to main storage in a tightly coupled multi-processing apparatus is disclosed. The system includes a plurality of central processing units (CPUs), a main storage unit commonly shared by the plurality of CPUs and a memory control unit operatively connected to each of the CPUs. A process for ensuring that a correct sequence of accesses to the main storage is followed is called a "serialization." When a serialization occurs subsequent to a "STORE" instruction in a particular CPU, the system for controlling a serialization notifies the occurrence of a serialization to all other CPUs before the particular CPU requests the memory control unit for the serialization. If the particular CPU is not notified of any occurrence of a serialization in the other CPUs, the particular CPU immediately executes the following "FETCH" operation without waiting for completion of the particular CPU's serialization. Even if notified of an occurrence of a serialization in the other CPUs, the particular CPU need only wait for completion of the other CPU's serialization to execute the following "FETCH". When a serialization does not occur in the particular CPU, serialization notifications by the other CPUs are disregarded.

Abstract translation: 公开了一种用于控制对紧密耦合的多处理设备中的主存储的访问进行“串行化”的系统和方法。 该系统包括多个中央处理单元（CPU），由多个CPU共同共享的主存储单元和可操作地连接到每个CPU的存储器控​​制单元。 确保遵循对主存储器的正确访问顺序的过程称为“序列化”。 当在特定CPU中的“存储”指令之后发生序列化时，用于控制串行化的系统在特定CPU请求存储器控制单元进行序列化之前，向所有其他CPU通知序列化的发生。 如果特定CPU没有被通知在其他CPU中发生串行化，则特定CPU立即执行以下“FETCH”操作，而不等待特定CPU串行化的完成。 即使通知其他CPU发生序列化，特定CPU只需要等待其他CPU的串行化完成以执行以下“FETCH”。 当特定CPU不发生序列化时，其他CPU的序列化通知将被忽略。

公开(公告)号：US07350062B2

公开(公告)日：2008-03-25

申请号：US11207825

申请日：2005-08-22

Applicant: Masaki Ukai ,  Kyoko Tashima ,  Aiichiro Inoue

Inventor： Masaki Ukai ,  Kyoko Tashima ,  Aiichiro Inoue

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/3844 ,  G06F9/3861

Abstract: An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a return address stack, of which the stack operation is activated at a time of completing execution of an subroutine call/return correspondent instruction and an entry designating unit (pointer), in order to adjust a time difference resulting from an instruction fetch being executed prior to completing an instruction, pointing to a position relative to the stack front and adjusting a time difference between an instruction fetch performed speculatively in advance and completion of an instruction both at a time of completing execution of a branch instruction that is correspondent to a subroutine call/return and at a time of predicting a subroutine call/return in synchrony to the instruction fetch. An entry position correspondent to a stack position pointed to by the entry designation unit is adopted as a subroutine call/return prediction address and consequently the prediction of the subroutine return address becomes more accurate and the processing speed becomes higher.

Abstract translation: 信息处理装置能够推测性地执行诸如流水线/超标量/无序执行并且配备有分支预测机制（分支历史）的执行。 信息处理装置为了处理包含子程序的高速指令序列，还配备有返回地址堆栈，其中堆栈操作在完成子程序调用/返回通讯器的执行时被激活 指令和条目指定单元（指针），以便调整在完成指令之前执行的指令提取导致的时间差，指向相对于堆栈前端的位置，并且调整在推测上执行的指令提取之间的时间差 在完成执行与子程序调用/返回相对应的分支指令时以及在与指令获取同步地预测子程序调用/返回时，提前执行指令并完成指令。 采用由入口指定单元指向的堆栈位置的入口位置作为子程序调用/返回预测地址，因此子程序返回地址的预测变得更准确，处理速度变高。