公开(公告)号：US20250046625A1

公开(公告)日：2025-02-06

申请号：US18733052

申请日：2024-06-04

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/82 ,  H01L23/31 ,  H01L23/528

Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

公开(公告)号：US20250038104A1

公开(公告)日：2025-01-30

申请号：US18759139

申请日：2024-06-28

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Rajesh Katkar ,  Belgacem Haba

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L25/16 ,  H01L29/94

Abstract: A component comprises a substrate comprising a first side and a second side opposite to the first side. A first dielectric layer is formed on the first side, and a plurality of electrically conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and a plurality of electrically conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening that extends at least partially from the first side towards the second side of the substrate. Each of the capacitors comprises at least three electrodes. At least one of the plurality of capacitors is coupled on the first side to an electrically conductive pad of the first dielectric layer and is coupled on the second side to an electrically conductive pad of the second dielectric layer.

公开(公告)号：US12191233B2

公开(公告)日：2025-01-07

申请号：US17876376

申请日：2022-07-28

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba ,  Thomas Workman ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Rajesh Katkar

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/32 ,  H01L23/467 ,  H01L23/473 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

公开(公告)号：US20250006689A1

公开(公告)日：2025-01-02

申请号：US18513145

申请日：2023-11-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Gaius Gillman Fountain, JR. ,  Thomas Workman ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L25/065

Abstract: Disclosed is a bonded structure including a substrate that includes a surface and at least one bumper extending above the surface by a bumper height. The bonded structure further includes at least one die directly bonded to the surface adjacent the bumper.

公开(公告)号：US20250006679A1

公开(公告)日：2025-01-02

申请号：US18391173

申请日：2023-12-20

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Jeremy Alfred Theil ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Belgacem Haba ,  Laura Wills Mirkarimi

IPC: H01L23/00

Abstract: A structure includes a first substrate including a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion and a second substrate including a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The structure further includes an interface layer having at least one electrically conductive oxide material between the first layer and the second layer. The at least one electrically conductive oxide material includes at least one first region between and in electrical communication with the at least one electrically conductive first portion and the at least one electrically conductive third portion, and at least one second region between the at least one electrically insulative second portion and the at least one electrically insulative fourth portion.

公开(公告)号：US20250004197A1

公开(公告)日：2025-01-02

申请号：US18745266

申请日：2024-06-17

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba ,  Rajesh Katkar ,  Mani Hossein-Zadeh

IPC: G02B6/12

Abstract: A directly bonded optical component comprising one or more optical channels is disclosed. The directly bonded optical component can include at least a first optical element and a second optical element directly bonded to the first optical element without an intervening adhesive. The optical component can include a first optical channel through at least a portion of the first optical element, the first optical channel extending between a first port at a first side of the optical component and a second port at a second side of the optical component. A second optical channel or waveguide can extend through at least a portion of the second optical element from a third port at the first side of the optical component to a fourth port. The first and third ports can be separated by a first distance and the second and fourth parts can be separated a second distance along an exterior surface of the optical component. The first distance can be different from the second distance.

公开(公告)号：US12183659B2

公开(公告)日：2024-12-31

申请号：US18397505

申请日：2023-12-27

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/427 ,  H01L23/467 ,  H01L25/18 ,  H10B80/00

Abstract: A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening disposed there through. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downward from the base surface, where the base surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.

公开(公告)号：US20240371850A1

公开(公告)日：2024-11-07

申请号：US18541869

申请日：2023-12-15

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Guilian Gao ,  Gaius Gillman Fountain, JR.

IPC: H01L25/00 ,  H01L21/18 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

公开(公告)号：US20240332227A1

公开(公告)日：2024-10-03

申请号：US18194544

申请日：2023-03-31

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Inventor： Cyprian Emeka Uzoh ,  Oliver Zhao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0543

Abstract: A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.

公开(公告)号：US20240312953A1

公开(公告)日：2024-09-19

申请号：US18671851

申请日：2024-05-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80143 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.