公开(公告)号：US11942182B2

公开(公告)日：2024-03-26

申请号：US18089668

申请日：2022-12-28

申请人： Rambus Inc.

发明人： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC分类号： G11C7/10 ,  G11C5/04

CPC分类号： G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

摘要： A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US11914508B2

公开(公告)日：2024-02-27

申请号：US17065082

申请日：2020-10-07

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Ely K. Tsern

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891 ,  G06F12/1009

CPC分类号： G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

摘要： A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US11889013B2

公开(公告)日：2024-01-30

申请号：US17685771

申请日：2022-03-03

申请人： Zoho Corporation Private Limited

发明人： Mathivanan Venkatachalam ,  Rajesh Ranganathan ,  Murugesan Duraipandi ,  Vishal Santharam

IPC分类号： H04M1/72415 ,  H04W4/14 ,  H04L51/18 ,  H04W12/04 ,  H04W4/12 ,  H04W88/04 ,  H04L61/00 ,  H04L67/125 ,  H04W8/24 ,  H04W12/033 ,  H04W12/61 ,  H04W12/126 ,  H04M1/72463 ,  H04L9/40

CPC分类号： H04M1/72415 ,  H04L51/18 ,  H04L61/00 ,  H04L67/125 ,  H04M1/72463 ,  H04W4/12 ,  H04W4/14 ,  H04W8/245 ,  H04W12/033 ,  H04W12/04 ,  H04W12/126 ,  H04W12/61 ,  H04W88/04 ,  H04L63/0442

摘要： An administrative or relay device can communicate with a target device, for example to disable lost or stolen devices using an SMS command. The SMS command is encrypted to prevent malicious attacks. The SMS command includes a universal device identifier unique to the target device, the phone number of the relaying device, and a time stamp memorializing command creation. The relaying device relays the encrypted command to the target device. Successful decryption authenticates the administrative or relay device. Before executing the command, however, the target device reviews the unique identifier to verify the target and compares the phone number of the relaying device with the number identified with the incoming SMS message to authenticate the relaying device. The target device also considers an embedded time stamp to determine whether the command is superseded by a subsequently issued though later received command.

公开(公告)号：US11782476B2

公开(公告)日：2023-10-10

申请号：US17529515

申请日：2021-11-18

申请人： Rambus Inc.

发明人： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC分类号： G06F1/10

CPC分类号： G06F1/10

摘要： A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

公开(公告)号：US11709736B2

公开(公告)日：2023-07-25

申请号：US17354268

申请日：2021-06-22

申请人： Rambus Inc.

发明人： Kenneth L. Wright ,  Frederick A. Ware

IPC分类号： G06F11/00 ,  G06F11/14 ,  H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  H01L25/065 ,  H01L25/10

CPC分类号： G06F11/142 ,  G06F3/0617 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/00 ,  G06F13/1673 ,  G06F13/4068 ,  H01L24/00 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  G06F11/1423 ,  G06F2201/805 ,  G06F2201/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/85399

摘要： A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US11558499B2

公开(公告)日：2023-01-17

申请号：US17361965

申请日：2021-06-29

申请人： Zoho Corporation Private Limited

发明人： Mathivanan Venkatachalam ,  Rajesh Ranganathan ,  Murugesan Duraipandi ,  Vishal Santharam ,  Arthur Behiel ,  Sudheer Grandhi

IPC分类号： H04W4/14 ,  H04W12/04 ,  H04W4/12 ,  H04W88/04 ,  H04W8/24 ,  H04W12/033 ,  H04W12/61 ,  H04W12/126 ,  H04M1/72415 ,  H04L51/18 ,  H04L61/00 ,  H04L67/125 ,  H04L9/40

摘要： An administrator can use an administrative-wireless-device to control a target wireless device using an SMS message to convey a command. The data of the command message can be encrypted to prevent malicious attacks. The encrypted data may include a universal device identifier unique to the target device, the phone number of the administrative-wireless-device, and a time stamp memorializing command or message creation. Before executing the command, however, the target device compares the phone number of the administrative-wireless-device with the number identified with the incoming SMS message to authenticate the administrative-wireless-device.

公开(公告)号：US11327831B2

公开(公告)日：2022-05-10

申请号：US16832263

申请日：2020-03-27

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John E. Linstadt ,  Liji Gopalakrishnan

IPC分类号： G06F11/10 ,  G06F3/06

摘要： A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

公开(公告)号：US11233589B2

公开(公告)日：2022-01-25

申请号：US17102779

申请日：2020-11-24

申请人： Rambus Inc.

发明人： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC分类号： H04B17/29 ,  H04L25/03 ,  H04L27/01 ,  H04B17/21 ,  G01R31/317 ,  H04L1/20 ,  H04L1/24 ,  H04L7/033 ,  G06F11/08 ,  H04L7/04 ,  H04L7/10

摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

公开(公告)号：US11211114B2

公开(公告)日：2021-12-28

申请号：US16503189

申请日：2019-07-03

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas J. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC分类号： G11C5/02 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

摘要： A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US11164622B2

公开(公告)日：2021-11-02

申请号：US17101574

申请日：2020-11-23

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC分类号： G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

摘要： Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.