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公开(公告)号：US11948607B2
公开(公告)日：2024-04-02
申请号：US18117603
申请日：2023-03-06
发明人： Hirofumi Kuribara
CPC分类号： G11B33/146 , G11B5/4813 , G11B19/2018 , G11B25/043
摘要： According to one embodiment, a disk device includes rotatable magnetic disks, a first actuator assembly rotatably supported on a pivot through a first bearing unit, a second actuator assembly rotatably supported on the pivot through a second bearing unit and provided side by side with the first actuator assembly in an axial direction of the pivot, and a filter unit provided between the magnetic disks and the first and second actuator assemblies. The filter unit includes a holder including a shielding portion facing a boundary portion between the first actuator assembly and the second actuator assembly and a ventilation opening provided at a position spaced apart from the boundary portion in the axial direction, and a filter held by the holder and facing the ventilation opening.
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公开(公告)号：US11947400B2
公开(公告)日：2024-04-02
申请号：US18200453
申请日：2023-05-22
申请人： Kioxia Corporation
发明人： Yoshihisa Kojima , Katsuhiko Ueki
CPC分类号： G06F1/263 , G06F12/0246 , G06F2212/2028 , G06F2212/205
摘要： In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
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公开(公告)号：US11942110B2
公开(公告)日：2024-03-26
申请号：US18119749
申请日：2023-03-09
发明人： Takashi Fujinami , Noriyuki Satou , Takashi Onoda
CPC分类号： G11B19/02
摘要： According to one embodiment, a magnetic disk device includes a disk, a head, a command queue, a command residence time calculation unit calculating a residence time of each of commands in the command queue, a command information calculation unit calculating the number of the commands and a ratio, a limit time determination unit obtaining a latency limit time corresponding to the number of commands and the ratio, from a latency limit time determination table, and a command selection processing unit selecting a command to be executed, by considering the latency limit time.
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公开(公告)号：US11923443B2
公开(公告)日：2024-03-05
申请号：US17469239
申请日：2021-09-08
发明人： Shoko Hanagata
IPC分类号： H01L29/739 , H01L29/08 , H01L29/861
CPC分类号： H01L29/7397 , H01L29/083 , H01L29/861
摘要： A semiconductor device in which IGBT regions and diode regions are alternately set along a first direction, includes first to third electrodes, and a semiconductor portion. The semiconductor portion includes a collector layer, a low-concentration cathode layer, a high-concentration cathode layer, a drift layer, anode layers, base layers, and an emitter layer. The low-concentration cathode layer and the high-concentration cathode layer are in contact with the first electrode. When the diode region on a lower surface of the semiconductor portion is divided into three equal regions of a first peripheral region, a central region, and a second peripheral region along the first direction, an area ratio of the low-concentration cathode layer in the central region is higher than the area ratio of the low-concentration cathode layer in the first peripheral region and the second peripheral region.
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公开(公告)号：US11923325B2
公开(公告)日：2024-03-05
申请号：US17695654
申请日：2022-03-15
申请人： Kioxia Corporation
发明人： Yasuhito Yoshimizu , Takashi Fukushima , Tatsuro Hitomi , Arata Inoue , Masayuki Miura , Shinichi Kanno , Toshio Fujisawa , Keisuke Nakatsuka , Tomoya Sanuki
IPC分类号： H01L23/00 , G06F11/07 , H01L23/544
CPC分类号： H01L24/05 , G06F11/073 , G06F11/0751 , H01L23/544 , H01L2223/5446 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2924/14511
摘要： A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
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公开(公告)号：US11916027B2
公开(公告)日：2024-02-27
申请号：US17016631
申请日：2020-09-10
发明人： Yoshihiko Fuji , Ryohei Nega , Tatsuya Ohguro , Takanobu Kamakura
CPC分类号： H01L23/645 , H01F27/2804 , H01L28/10 , H01F2027/2809
摘要： According to one embodiment, an isolator includes first and second electrodes, first and second insulating portions, and a first dielectric portion. The first insulating portion is provided on the first electrode. The second electrode is provided on the first insulating portion. The second insulating portion is provided around the second electrode along a first plane perpendicular to a first direction. The second insulating portion contacts the second electrode. The first dielectric portion is provided between the first and second insulating portions. At least a portion of the first dielectric portion contacts the second electrode and is positioned around the second electrode along the first plane. A distance between a lower end of the second electrode and a first interface between the first dielectric portion and the second insulating portion is less than a distance between the first interface and an upper end of the second electrode.
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公开(公告)号：US11908526B2
公开(公告)日：2024-02-20
申请号：US17589365
申请日：2022-01-31
申请人： Kioxia Corporation
发明人： Naoto Kumano , Kenji Sakurada
CPC分类号： G11C16/26 , G06F11/1004 , G11C16/0483 , H10B69/00
摘要： According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.
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公开(公告)号：US11880592B2
公开(公告)日：2024-01-23
申请号：US17549440
申请日：2021-12-13
申请人： Kioxia Corporation
发明人： Takeshi Kikuchi
IPC分类号： G06F3/06
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0619 , G06F3/0659 , G06F3/0679
摘要： According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller communicates with a host. The host includes a host memory and a circuit. The circuit accesses the host memory in a unit of first size. When an address designated as a first location of the host memory where data read from the nonvolatile memory is to be stored is not aligned with a boundary in the host memory defined in a unit of the first size, the controller transmits a first packet which has a size from the first location to the boundary and includes the read data to be stored from the first location, and transmits a second packet which has the first size and includes the read data to be stored from the boundary thereafter.
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公开(公告)号：US11861194B2
公开(公告)日：2024-01-02
申请号：US17735858
申请日：2022-05-03
申请人： Kioxia Corporation
发明人： Hiroshi Isozaki , Teruji Yamakawa
IPC分类号： G06F3/06
CPC分类号： G06F3/0637 , G06F3/067 , G06F3/0622 , G06F3/0626 , G06F3/0652 , G06F3/0659 , G06F3/0673
摘要： According to one embodiment, a storage device is configured to store unencrypted user data. The user data is erased according to at least one data erasure mechanism. The storage device comprises a receiver configured to receive an inquiry from a host device, and a transmitter configured to transfer response information indicating the at least one data erasure mechanism to the host device.
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公开(公告)号：US11860264B2
公开(公告)日：2024-01-02
申请号：US17005840
申请日：2020-08-28
CPC分类号： G01S13/36 , G01S13/84 , G01S13/788
摘要： A ranging apparatus of an embodiment is a ranging apparatus adopting communication type ranging by a phase detection scheme. The ranging apparatus including: a transmitting circuit configured to be able to transmit by a plurality of channels used for data communication and configured to transmit a transmission signal obtained by modulating transmission data; and a control circuit configured to control the transmission circuit to cause a plurality of continuous waves having mutually different frequencies to be generated in a same channel as continuous waves used for ranging by the phase detection scheme.
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