公开(公告)号：US11131693B2

公开(公告)日：2021-09-28

申请号：US16717802

申请日：2019-12-17

Applicant: Vishay-Siliconix, LLC.

Inventor： M. Ayman Shibib ,  Wenjie Zhang

IPC: G01R19/00 ,  H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  G01R19/15 ,  H01L21/8234 ,  H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.

公开(公告)号：US11004841B2

公开(公告)日：2021-05-11

申请号：US16379609

申请日：2019-04-09

Applicant: VISHAY-SILICONIX

Inventor： Chanho Park ,  Ayman Shibib ,  Kyle Terrill

IPC: H01L27/02 ,  H01L21/48 ,  H01L23/60 ,  H01L21/66 ,  H01L23/00

Abstract: Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged.

公开(公告)号：US10651303B2

公开(公告)日：2020-05-12

申请号：US16291996

申请日：2019-03-04

Applicant: Vishay-Siliconix

Inventor： Ayman Shibib ,  Kyle Terrill

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/8252 ,  H01L29/423 ,  H01L29/861 ,  H01L29/20 ,  H01L29/10 ,  H01L29/207

Abstract: A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.

公开(公告)号：US10600902B2

公开(公告)日：2020-03-24

申请号：US12030719

申请日：2008-02-13

Applicant: Robert Xu

Inventor： Robert Xu

IPC: H01L27/06 ,  H01L29/78 ,  H01L23/525 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/808

Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.

公开(公告)号：US10527654B2

公开(公告)日：2020-01-07

申请号：US15634739

申请日：2017-06-27

Applicant: Vishay-Siliconix

Inventor： M. Ayman Shibib ,  Wenjie Zhang

IPC: G01R19/00 ,  H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  G01R19/15 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.

公开(公告)号：US10444262B2

公开(公告)日：2019-10-15

申请号：US15634901

申请日：2017-06-27

Applicant: Vishay-Siliconix

Inventor： M. Ayman Shibib ,  Wenjie Zhang

IPC: G01R19/00 ,  H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  G01R19/15 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, a semiconductor device includes a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET). The main-MOSFET includes a plurality of parallel main trenches, wherein the main trenches comprise a first electrode coupled to a gate of the main-MOSFET, and a plurality of main mesas between the main trenches, wherein the main mesas comprise a main source and a main body of the main-MOSFET. The semiconductor device also includes a sense-diode. The sense-diode includes a plurality of sense-diode trenches, wherein each of the sense-diode trenches comprises a portion of one of the main trenches, and a plurality of sense-diode mesas between the source-FET trenches, wherein the sense-diode mesas comprise a sense-diode anode that is electrically isolated from the main source of the main-MOSFET.

公开(公告)号：US10224426B2

公开(公告)日：2019-03-05

申请号：US15643306

申请日：2017-07-06

Applicant: Vishay-Siliconix

Inventor： Ayman Shibib ,  Kyle Terrill

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/861 ,  H01L29/20 ,  H01L29/10 ,  H01L29/207

Abstract: A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.

公开(公告)号：US10084037B2

公开(公告)日：2018-09-25

申请号：US15339678

申请日：2016-10-31

Applicant: VISHAY-SILICONIX

Inventor： Qufei Chen ,  Kyle Terrill ,  Sharon Shi

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

公开(公告)号：US09887259B2

公开(公告)日：2018-02-06

申请号：US14659394

申请日：2015-03-16

Applicant: Vishay-Siliconix

Inventor： Deva Pattanayak ,  Olof Tornblad

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802

Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.

公开(公告)号：US09673314B2

公开(公告)日：2017-06-06

申请号：US14794164

申请日：2015-07-08

Applicant: Vishay-Siliconix

Inventor： Chanho Park ,  Ayman Shibib ,  Kyle Terrill

IPC: H01L29/76 ,  H01L29/40 ,  H01L27/095 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/872

Abstract: A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.