公开(公告)号：US20030190781A1

公开(公告)日：2003-10-09

申请号：US10305437

申请日：2002-11-26

Applicant: SGS-Thomson Microelectronics, Inc.

Inventor： Robert Louis Hodges ,  Loi Ngoc Nguyen

IPC: H01L021/8234 ,  H01L021/3205 ,  H01L029/76

CPC classification number: H01L21/76897 ,  H01L21/768 ,  H01L27/105 ,  H01L29/6659

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract translation: 一种集成电路存储器制造工艺和结构，其中在存储器芯片的外围（以及可选地在地线上）执行腐蚀，而不是存储在存储器单元的晶体管上。

公开(公告)号：US6064109A

公开(公告)日：2000-05-16

申请号：US475178

申请日：1995-06-07

Applicant: Richard A. Blanchard ,  William P. Imhauser

Inventor： Richard A. Blanchard ,  William P. Imhauser

IPC: H01L21/331 ,  H01L29/73 ,  H01L27/082

CPC classification number: H01L29/66303 ,  H01L29/7304

Abstract: A semiconductor device includes an emitter region, a contact region, and a resistive medium. The resistive medium is connected between the contact region and the emitter region. The contact region and the emitter region each include an edge facing each other. At least a portion of the emitter region edge and at least a portion of the contact region edge are non-parallel relative to each other. This configuration enables an emitter ballast resistance to be provided with varied emitter current flow along the injecting edge of the emitter. Furthermore, by including an additional contact and an additional resistive medium between the contacts, the ballast resistance of the semiconductor device can be increased without decreasing the figure of merit of the device.

Abstract translation: 半导体器件包括发射极区域，接触区域和电阻介质。 电阻介质连接在接触区域和发射极区域之间。 接触区域和发射极区域各自包括彼此面对的边缘。 发射极区域边缘的至少一部分和接触区域边缘的至少一部分相对于彼此不平行。 这种配置使发射极镇流电阻能够沿发射极的注入边缘提供变化的发射极电流。 此外，通过在触点之间附加附加触点和附加电阻介质，可以增加半导体器件的镇流电阻，而不会降低器件的品质因数。

公开(公告)号：US06014050A

公开(公告)日：2000-01-11

申请号：US801452

申请日：1997-02-18

Applicant: David Charles McClure

Inventor： David Charles McClure

IPC: G01R31/28 ,  H01L21/822 ,  H01L27/04 ,  H03K5/04 ,  H03K5/13

CPC classification number: H03K5/133

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract translation: 根据本发明，通过将一个或多个延迟信号的逻辑状态设置为适当的值，可以修改整个具有分布式电路块的集成电路中的多个电源延迟元件的电阻值，以产生所需的延迟时间或脉冲 整个集成电路的宽度调整。 将延迟信号设置到所需逻辑状态可以通过各种手段来实现，包括强制测试焊盘达到逻辑电平，熔断熔丝或进入测试模式。

公开(公告)号：US5825060A

公开(公告)日：1998-10-20

申请号：US869517

申请日：1992-04-16

Applicant: Charles R. Spinner, III

Inventor： Charles R. Spinner, III

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112

Abstract: A resistor structure suitable for use in an SRAM cell is formed from polycrystalline silicon elements. These elements have a cross-section which is less than is normally available for polycrystalline silicon interconnect lines, allowing increased resistance values to be implemented using a lesser amount of surface area. In one embodiment of a resistor, sidewall spacers are formed in a cavity within an insulating layer, and polycrystalline silicon resistive elements are formed in the narrowed region within the cavity. In another embodiment, polycrystalline silicon resistors alongside vertical sidewalls of a cavity are formed using sidewall spacer technology. In either event, the cross-sectional area of the resistors is less than that normally available for a given processing technology, resulting in enhanced resistor values.

Abstract translation: 适用于SRAM单元的电阻结构由多晶硅元件形成。 这些元件具有小于通常可用于多晶硅互连线的横截面，允许使用较少量的表面积来实现增加的电阻值。 在电阻器的一个实施例中，侧壁间隔物形成在绝缘层内的空腔中，并且多晶硅电阻元件形成在空腔内的变窄区域中。 在另一个实施例中，使用侧壁间隔物技术形成沿着空腔的垂直侧壁的多晶硅电阻器。 在任一情况下，电阻器的横截面积小于通常用于给定处理技术的横截面积，导致增强的电阻值。

公开(公告)号：US5818292A

公开(公告)日：1998-10-06

申请号：US859305

申请日：1996-04-02

Applicant: William Carl Slemmer

Inventor： William Carl Slemmer

IPC: G05F3/26 ,  G05F3/30 ,  G11C5/14

CPC classification number: G11C5/143 ,  G05F3/30 ,  G05F3/267

Abstract: According to the present invention, a circuit, utilizing a minimum number of bipolar devices and current mirror scaling devices, generates a bandgap reference voltage. The bandgap voltage generated by the bandgap reference circuit is a function of a plurality of sized current mirror devices, the ratio of a first resistor to a second resistor, and the number and relative sizing of bipolar junction transistors used. The bandgap reference circuit generates a bandgap reference voltage which is suitable for use in a variety of integrated circuit devices, such as a zero power static random access memory (SRAM). If used in a zero power SRAM application, the bandgap reference voltage may be utilized to determine when the primary power source of the zero power SRAM has fallen below a predetermined voltage level and a secondary power source must be substituted for the primary power source.

Abstract translation: 根据本发明，利用最小数量的双极器件和电流镜放大装置的电路产生带隙参考电压。 由带隙参考电路产生的带隙电压是多个尺寸的电流镜器件的函数，第一电阻器与第二电阻器的比率以及所使用的双极结型晶体管的数量和相对尺寸。 带隙基准电路产生适用于诸如零功率静态随机存取存储器（SRAM）的各种集成电路器件的带隙基准电压。 如果在零功率SRAM应用中使用，则可利用带隙参考电压来确定零功率SRAM的主电源何时已经降至低于预定电压电平，并且次级电源必须代替主电源。

公开(公告)号：US5805523A

公开(公告)日：1998-09-08

申请号：US825971

申请日：1997-04-04

Applicant: Mark A. Lysinger

Inventor： Mark A. Lysinger

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  G11C11/41 ,  G11C8/00

CPC classification number: G11C7/1018

Abstract: The decoded address signal is stored in the slave latch. The output of the slave latch is a column select signal. The slave latches are organized in a slave latch circuit which is connected as a counter. Each of the slave latches is treated as a register and four slave latches are combined to permit the sequential addresses selected to be in count up or count down as the slave latch circuit is clocked. In addition, a burst counter control circuit selectively controls the counter to produce a count in an interleaved mode or a count up mode. The least significant bit of the address is stored within the burst control circuit for indicating whether the count should be an up count or a down count when operating in the interleaved mode.

Abstract translation: 解码的地址信号被存储在从锁存器中。 从锁存器的输出是列选择信号。 从锁存器组织在作为计数器连接的从锁存电路中。 每个从锁存器被视为寄存器，并且组合四个从锁存器，以允许所选择的顺序地址在从锁存电路被计时时被递增计数或递减计数。 此外，突发计数器控制电路选择性地控制计数器以产生交错模式或递增计数模式的计数。 地址的最低有效位被存储在突发控制电路内，用于指示当以交织模式操作时计数应该是递增计数还是递减计数。

公开(公告)号：US5805027A

公开(公告)日：1998-09-08

申请号：US642271

申请日：1996-05-03

Applicant: Rong Yin

Inventor： Rong Yin

IPC: H03K3/014 ,  H03K3/354 ,  H03B5/06 ,  H03B5/36

CPC classification number: H03K3/014 ,  H03K3/3545

Abstract: Crystal oscillator circuitry provides a very fast start-up function requiring less than 100 mS. The crystal oscillator circuitry enters a stop mode when a control signal transitions from a first logic level to a second logic level thereby causing a crystal to stop oscillating. In order to initiate the fast start-up function, a pulse is provided to the gate of a transistor which is electrically connected between a first node and a second node, thus causing the voltage of the first node to move towards the voltage level of the second node and the second node to move towards the voltage level of the first node. Upon initiation of the start-up function, the energy at the crystal of the crystal oscillator circuitry is at least four times higher than the energy required in a steady state mode. The crystal oscillator circuitry has a VT (threshold voltage) independent high feedback resistance which provides stable oscillation frequency over a wide range of Vcc supply voltage. The VT independent high feedback resistance is ensured by proper sizing of the transistors of the crystal oscillator circuitry.

Abstract translation: 晶体振荡器电路提供非常快的启动功能，需要小于100 mS。 当控制信号从第一逻辑电平转换到第二逻辑电平时，晶体振荡器电路进入停止模式，从而导致晶体停止振荡。 为了启动快速启动功能，将脉冲提供给电连接在第一节点和第二节点之间的晶体管的栅极，从而使得第一节点的电压朝向 第二节点和第二节点朝向第一节点的电压电平移动。 在起动功能开始时，晶体振荡器电路的晶体的能量比稳定状态模式中所需的能量高至少四倍。 晶体振荡器电路具有独立的VT（阈值电压）独立的高反馈电阻，可在宽范围的Vcc电源电压下提供稳定的振荡频率。 通过晶体振荡器电路的晶体管的适当尺寸确保VT独立的高反馈电阻。

公开(公告)号：US5801563A

公开(公告)日：1998-09-01

申请号：US588988

申请日：1996-01-19

Applicant: David Charles McClure

Inventor： David Charles McClure

IPC: H03K5/1252 ,  H03K19/00 ,  H03K19/0175 ,  H03K5/12 ,  H03K17/687

CPC classification number: H03K19/0013

Abstract: An output driver circuit an integrated circuit memory device prevents crowbar currents from occurring. The output driver uses just one resistive element having multiple taps so that the amount of silicon area used for slew rate control is minimized. The signals which control the output driver devices are carefully balanced for no skew and cross at a voltage level of Vcc/2 so that there is no crowbar current generated during tri-stating of the output driver output signal.

Abstract translation: 输出驱动器电路集成电路存储器件防止发生撬棒电流。 输出驱动器仅使用具有多个抽头的一个电阻元件，使得用于转换速率控制的硅面积的量被最小化。 控制输出驱动器器件的信号在Vcc / 2的电压电平下不会出现偏斜和交叉，因此在输出驱动器输出信号三态期间不产生紧急电流。

公开(公告)号：US5801553A

公开(公告)日：1998-09-01

申请号：US709478

申请日：1996-09-05

Applicant: Eric J. Danstrom

Inventor： Eric J. Danstrom

IPC: H03K3/2897 ,  H03K3/0233 ,  H03K3/353 ,  H03K5/08 ,  H03K5/24 ,  H03K17/22 ,  H03K5/22

CPC classification number: H03K17/223 ,  H03K17/22 ,  H03K3/02337 ,  H03K5/2418 ,  H03K5/2445 ,  H03K2017/226

Abstract: A comparator with a built-in hysteresis is disclosed. The comparator has a differential input stage, an output stage, and a bias circuit with a hysteresis circuit. The hysteresis circuit selectively applies a bias voltage to the differential input stage to achieve the hysteresis.

公开(公告)号：US5796545A

公开(公告)日：1998-08-18

申请号：US484495

申请日：1995-06-07

Applicant: Athos Canclini

Inventor： Athos Canclini

IPC: G11B5/54 ,  G11B5/55 ,  G11B5/596 ,  G11B19/24 ,  G11B21/02 ,  G11B21/08 ,  H03H11/02 ,  H04L25/02 ,  H04L29/02

CPC classification number: G11B5/59622 ,  G11B19/24 ,  G11B21/02 ,  G11B21/08 ,  G11B21/083 ,  G11B5/54 ,  G11B5/5526 ,  G11B5/553

Abstract: A control circuit for providing a stable, adjustable, time constant for use as a master time constant is presented. Used as a master time-constant circuit, this control circuit can ensure multiple slave circuits are precisely calibrated. The circuit includes a charging section that receives a series of calibrating pulses. The reference cell's voltage is compared to a reference voltage equal of Vcc/e. If the cell's voltage is below the reference voltage, a current source charges a capacitor, lowering the resistance of the transistor in the cell to correct the time circuit inaccuracy. Conversely, if the cell's voltage is above the reference voltage, a current sink discharges the capacitor, raising the transistor's resistance. This also corrects the time circuit inaccuracy. Thus, this circuit includes a method to correct time-constants which are too large or too small. This circuit is used in various applications where extreme accuracy and precision is needed, such as media drive read/write heads.

Abstract translation: 提供了一种用于提供用作主时间常数的稳定，可调节的时间常数的控制电路。 作为主时钟常数电路，该控制电路可以确保多个从电路精确校准。 该电路包括一个接收一系列校准脉冲的充电部分。 参考电池的电压与等于Vcc / e的参考电压进行比较。 如果电池的电压低于参考电压，则电流源对电容器充电，降低电池中晶体管的电阻，以校正电路不准确度。 相反，如果电池的电压高于参考电压，则电流吸收器对电容器进行放电，从而提高晶体管的电阻。 这也纠正了时间电路的不准确性。 因此，该电路包括校正太大或太小的时间常数的方法。 该电路用于需要极高精度和精度的各种应用，如介质驱动读/写头。