公开(公告)号：US11997306B2

公开(公告)日：2024-05-28

申请号：US18184524

申请日：2023-03-15

申请人： NVIDIA Corp.

发明人： Johan Pontus Andersson ,  Jim Nilsson ,  Tomas Guy Akenine-Möller

IPC分类号： H04N19/132 ,  G06T15/06 ,  H04N19/182 ,  H04N19/423 ,  H04N19/513

CPC分类号： H04N19/513 ,  G06T15/06 ,  H04N19/132 ,  H04N19/182 ,  H04N19/423

摘要： A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.

公开(公告)号：US11973501B2

公开(公告)日：2024-04-30

申请号：US17730352

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： H03K19/1776 ,  H03K19/17736 ,  H03K19/17784

CPC分类号： H03K19/1776 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17784

摘要： A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US20240094291A1

公开(公告)日：2024-03-21

申请号：US17932808

申请日：2022-09-16

申请人： NVIDIA Corp.

发明人： Mahmut Yilmaz ,  Vinod Pagalone ,  Munish Aggarwal ,  Doochul Shin

IPC分类号： G01R31/3185 ,  G01R31/317

CPC分类号： G01R31/318536 ,  G01R31/31727 ,  G01R31/318597

摘要： A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.

公开(公告)号：US20240030916A1

公开(公告)日：2024-01-25

申请号：US17932052

申请日：2022-09-14

申请人： NVIDIA Corp.

发明人： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC分类号： H03K19/0185 ,  H03K19/00

CPC分类号： H03K19/018521 ,  H03K19/0013 ,  H03K3/356165

摘要： A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US20240013033A1

公开(公告)日：2024-01-11

申请号：US18163603

申请日：2023-02-02

申请人： NVIDIA Corp.

发明人： Haoyu Yang ,  Haoxing Ren

IPC分类号： G06N3/0464 ,  G03F1/36

CPC分类号： G06N3/0464 ,  G03F1/36

摘要： A circuit mask optimizer utilizes a Convolutional Fourier Neural Operator (CFNO) to efficiently learn layout tile dependencies, enabling stitch-less largescale mask optimization with limited intervention of legacy tools. Litho-guided self training via a trained machine learning model provides non-convex optimization, enabling iterative model and dataset refinements at a substantial performance improvement over conventional solutions.

公开(公告)号：US20230363085A1

公开(公告)日：2023-11-09

申请号：US17737333

申请日：2022-05-05

申请人： NVIDIA Corp.

发明人： MingYi Yu ,  Greg Bodi ,  Ananta Attaluri

IPC分类号： H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01L23/36 ,  H01L23/498 ,  H01L23/50

CPC分类号： H05K1/0262 ,  H05K1/181 ,  H05K3/3436 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/50 ,  H05K2201/10734 ,  H05K2201/10704

摘要： A circuit system includes an integrated circuit package mounted on a first side of a printed circuit board and a power regulator connected to power terminals of the integrated circuit package through a cutout in the printed circuit board. The power regulator draws power from the printed circuit board by way of connections on a shelf region extending beyond an area of the cutout.

公开(公告)号：US20230353155A1

公开(公告)日：2023-11-02

申请号：US17730352

申请日：2022-04-27

申请人： NVIDIA Corp.

发明人： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir

IPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17736

CPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17744 ,  H03K19/1774

摘要： A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

公开(公告)号：US11804708B2

公开(公告)日：2023-10-31

申请号：US16812048

申请日：2020-03-06

申请人： NVIDIA Corp.

发明人： Jauwen Chen ,  Sunitha Venkataraman ,  Ting Ku

IPC分类号： H02H9/04 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0255 ,  H01L27/0277 ,  H01L27/0281

摘要： An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.

公开(公告)号：US11798923B2

公开(公告)日：2023-10-24

申请号：US17553519

申请日：2021-12-16

申请人： NVIDIA Corp.

发明人： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC分类号： H01L23/538 ,  H01L25/10 ,  H01L25/16 ,  H05K1/18

CPC分类号： H01L25/105 ,  H01L23/5386 ,  H01L25/16 ,  H05K1/181 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704

摘要： Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

公开(公告)号：US11630312B2

公开(公告)日：2023-04-18

申请号：US17367872

申请日：2021-07-06

申请人： NVIDIA Corp.

发明人： Jonghyun Kim ,  Youngmo Jeong ,  Michael Stengel ,  Morgan McGuire ,  David Luebke

IPC分类号： G02B27/01 ,  G03H1/22

摘要： An augmented reality display system includes a first beam path for a foveal inset image on a holographic optical element, a second beam path for a peripheral display image on the holographic optical element, and pupil position tracking logic that generates control signals to set a position of the foveal inset as perceived through the holographic optical element, to determine the peripheral display image, and to control a moveable stage.