公开(公告)号：US09412433B2

公开(公告)日：2016-08-09

申请号：US14161655

申请日：2014-01-22

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Donald Martin Morgan

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/40611

Abstract: A DRAM includes: a temperature sensor for monitoring a temperature operating condition of the DRAM; and a binary counter coupled to the temperature sensor, for receiving external commands to perform a refresh operation, and incrementing a count upon each received external command, wherein the refresh operation will be selectively skipped according to a value of the binary counter. The binary counter is activated to a first mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a first threshold and activated to a second mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a second threshold lower than the first threshold.

Abstract translation: DRAM包括：用于监视DRAM的温度操作状态的温度传感器; 以及耦合到所述温度传感器的二进制计数器，用于接收执行刷新操作的外部命令，以及在每个所接收的外部命令时递增计数，其中根据二进制计数器的值选择性地跳过刷新操作。 当温度传感器确定DRAM的温度操作条件低于第一阈值时，二进制计数器被激活到第一模式，并且当温度传感器确定DRAM的温度操作条件低于第二阈值时激活到第二模式 比第一个门槛。

公开(公告)号：US09091929B2

公开(公告)日：2015-07-28

申请号：US14249371

申请日：2014-04-10

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chun-Wei Wu

IPC: G03F7/20 ,  G03F1/50

CPC classification number: G03F7/2022 ,  G03F1/50 ,  G03F7/203 ,  G03F7/70458 ,  G03F7/70466

Abstract: A method of forming a tight-pitched pattern. A target pattern including a plurality of first stripe patterns is provided. Each of the first stripe patterns has a first width and a first length. A photomask includes a plurality of second stripe patterns corresponding to the first stripe patterns is provided. Each of the second stripe patterns has a second width and a second length. A first exposure process with the photomask is provided in an exposure system. The first exposure process uses a first light source with a higher resolution that is capable of resolving the second width of each of the second stripe patterns. Finally, a second exposure process with the photo-mask is provided in the exposure system. The second exposure process uses a second light source with a lower resolution that is not adequate to resolve the second width of each of the second stripe patterns.

Abstract translation: 形成紧斜图案的方法。 提供包括多个第一条纹图案的目标图案。 每个第一条纹图案具有第一宽度和第一长度。 光掩模包括与第一条纹图案相对应的多个第二条纹。 每个第二条纹图案具有第二宽度和第二长度。 在曝光系统中提供了具有光掩模的第一曝光过程。 第一曝光过程使用具有更高分辨率的第一光源，其能够分辨每个第二条纹图案的第二宽度。 最后，在曝光系统中提供具有光掩模的第二曝光处理。 第二曝光过程使用具有较低分辨率的第二光源，其不足以解决每个第二条纹图案的第二宽度。

公开(公告)号：US09070584B2

公开(公告)日：2015-06-30

申请号：US13901592

申请日：2013-05-24

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shyam Surthi ,  Lars Heineck

IPC: H01L27/108 ,  H01L23/522

CPC classification number: H01L27/10894 ,  H01L23/5225 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.

Abstract translation: 存储器阵列包括沿着第一方向延伸的多个数字线（DL）沟槽; DL沟槽之间的埋置数字线; 密封每个DL沟槽中的气隙的沟槽填充材料层; 沿着第二方向延伸的多个字线（WL）沟槽; 设置在埋地数字线一端的有源斩波（AC）沟槽; 气隙中的屏蔽层; 以及围绕AC沟槽的侧壁的侧壁导体。

公开(公告)号：US09041154B2

公开(公告)日：2015-05-26

申请号：US13786463

申请日：2013-03-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chien-An Yu ,  Chih-Huang Wu

IPC: H01L29/00 ,  H01L27/04 ,  H01L23/522 ,  H01L27/06 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L27/04 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/91 ,  H01L2924/0002 ,  Y10S257/906 ,  H01L2924/00

Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.

Abstract translation: 半导体存储器件包括其上具有存储器阵列区域和外围电路区域的衬底。 第一电介质层覆盖衬底上的存储器阵列区域和外围电路区域。 第二电介质层覆盖第一电介质层上的存储器阵列区域和外围电路区域。 在存储器阵列区域中至少提供一个电容器结构。 电容器结构包括嵌入在第二电介质层中的电极材料层。 半导体存储器件还包括包括电极材料层的接触结构。

公开(公告)号：US09041099B2

公开(公告)日：2015-05-26

申请号：US13084533

申请日：2011-04-11

Applicant: Shyam Surthi ,  Sheng-Wei Yang

Inventor： Shyam Surthi ,  Sheng-Wei Yang

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a single-sided access device including an active fin structure comprising a source region and a drain region; an insulating layer interposed between the source region and the drain region; a trench isolation structure disposed at one side of the active fin structure; a single-sided sidewall gate electrode disposed on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by trench isolation structure and the single-sided sidewall gate electrode; and a gate protrusion laterally and electrically extended from the single-sided sidewall gate electrode and embedded between the source region and the drain region under the insulating layer.

Abstract translation: 本发明提供了一种包括源极区和漏极区的有源鳍结构的单面存取装置。 介于所述源极区域和所述漏极区域之间的绝缘层; 设置在所述活动鳍结构的一侧的沟槽隔离结构; 设置在与沟槽隔离结构相对的有源鳍结构的另一侧的单面侧壁栅电极，使得活性鳍结构被沟槽隔离结构和单侧壁栅电极夹在中间; 以及从所述单面侧壁栅电极侧向和电气地延伸并且嵌入在所述绝缘层下方的所述源极区域和所述漏极区域之间的栅极突起。

公开(公告)号：US20150067197A1

公开(公告)日：2015-03-05

申请号：US14017277

申请日：2013-09-03

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Timothy M. Hollis ,  Jeffrey P. Wright ,  Kang-Yong Kim ,  Eric J. Stave

IPC: G06F3/06

CPC classification number: G06F13/00 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0683 ,  G06F12/00 ,  G11C11/40 ,  G11C29/022 ,  G11C29/50012

Abstract: A memory structure that can perform characterization of output data paths without accessing the main memory array includes: a plurality of output data paths; a plurality of registers coupled to the output data paths. The registers include: at least a first pattern register and a second pattern register, for respectively storing a first data pattern and a second data pattern; and at least a first mapping register, for storing a plurality of binary values, wherein each binary value indicates whether the first data pattern or the second data pattern should be mapped to a corresponding output data path.

Abstract translation: 可以在不访问主存储器阵列的情况下执行输出数据路径的表征的存储器结构包括：多个输出数据路径; 耦合到输出数据路径的多个寄存器。 寄存器包括：至少第一模式寄存器和第二模式寄存器，用于分别存储第一数据模式和第二数据模式; 以及至少第一映射寄存器，用于存储多个二进制值，其中每个二进制值指示第一数据模式或第二数据模式是否应映射到相应的输出数据路径。

公开(公告)号：US20150056810A1

公开(公告)日：2015-02-26

申请号：US13974032

申请日：2013-08-22

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Vinay Nair ,  Lars Heineck

IPC: H01L21/308

CPC classification number: H01L21/3088 ,  H01L21/0337

Abstract: The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. The oxide layer is etched into spacers forming a first pattern that is then etched into the third layer. A second cross pattern is formed the same way on the third layer. Finally the first and second layers are etched with selectivity both patterns.

Abstract translation: 本发明提供一种用于形成接触印刷掩模的交叉双间距图案化方法。 首先，连续沉积第一层，第二层和第三层; 光致抗蚀剂沉积在第三层上，然后被修整成第一预图案，其上沉积有氧化物层。 将氧化物层蚀刻成形成第一图案的间隔物，然后将其蚀刻到第三层中。 在第三层上以相同的方式形成第二十字图案。 最后，选择性地蚀刻第一层和第二层两种图案。

公开(公告)号：US08916392B2

公开(公告)日：2014-12-23

申请号：US13902877

申请日：2013-05-27

Applicant: Nanya Technology Corp.

Inventor： Chun-I Hsieh ,  Chang-Rong Wu

IPC: H01L21/00 ,  H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/308 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.

Abstract translation: 磁阻随机存取存储器（MRAM）元件包括嵌入第一绝缘层中的底电极; 在所述第一绝缘层上的第二绝缘层的第一通孔中的环形参考层，所述环形参考层位于所述底部电极的上方; 填充第一通孔的第一间隙填充材料层; 覆盖所述环形基准层，所述第二绝缘层和所述第一间隙填充材料层的阻挡层; 在所述第二绝缘层上的第三绝缘层的第二通孔中的环形自由层，所述环形自由层位于所述环形参考层的上方; 以及堆叠在环形自由层上的顶部电极。

公开(公告)号：US08865550B2

公开(公告)日：2014-10-21

申请号：US14184725

申请日：2014-02-20

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/66 ,  H01L29/66 ,  H01L27/108 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

公开(公告)号：US20140213027A1

公开(公告)日：2014-07-31

申请号：US14184725

申请日：2014-02-20

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

Abstract translation: 提供一种形成掩埋位线的方法。 提供衬底并且在衬底中限定线状沟槽区域。 在基板的线状沟槽区域中形成线状沟槽。 线状沟槽包括侧壁表面和底部表面。 然后，将线状沟槽的底面加宽，形成弯曲的底面。 接下来，在与该弯曲底面相邻的基板上形成掺杂区域。 最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。