公开(公告)号：US20200097353A1

公开(公告)日：2020-03-26

申请号：US16609409

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Nathan Heldt-Sheller

IPC: G06F11/07 ,  G06F1/24 ,  G06F21/53 ,  G06F21/57 ,  G06F21/31 ,  G06F9/4401 ,  H04L29/08

Abstract: Various systems and methods for implementing a soft reset state. A server device includes processing circuitry; and at least one storage device including instructions embodied thereon, wherein the instructions, which when executed by the processing circuitry, configure the processing circuitry to perform operations of a soft reset operation, the operations to: define a soft reset state; cause a check of a secure virtual resource (SVR) of the server device, while in the soft reset state; and transition from the soft reset state in response to an event.

公开(公告)号：US10592354B2

公开(公告)日：2020-03-17

申请号：US15968130

申请日：2018-05-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Darwin Ou-Yang ,  Oleg Kagan ,  Sameer Chetan Saiya ,  Ravinder S. Thind

IPC: G06F11/14 ,  G06F3/06 ,  G06F9/44 ,  G06F1/24 ,  G06F9/4401

Abstract: In a first area of a persistent memory, data is stored that defines a known good state that is operable to launch the computing device to the known good state in response to a reboot. In response to a write request to the first area of persistent memory, the requested write is directed to a second area of the persistent memory and a record of redirected writes to the second area of persistent memory is updated. A request is received to establish an update to the known good state. The updated known good state is operable to launch the computing device to the updated known good state in response to a reboot. In response to the request, the record is persisted such that in response to a reboot, the record is usable to restore the redirected writes, thereby launching the computing device to the updated known good state.

公开(公告)号：US10572390B2

公开(公告)日：2020-02-25

申请号：US15273413

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F12/1009 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14 ,  G06F3/06

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US10571982B2

公开(公告)日：2020-02-25

申请号：US15819204

申请日：2017-11-21

Applicant: International Business Machines Corporation

Inventor： John Eells

IPC: G06F1/24 ,  G06F12/02 ,  G06F9/44 ,  G06F9/4401 ,  G06F8/65

Abstract: Embodiments include method, systems and computer program products for operating a resettable write once read many (RWORM) memory. The method includes receiving, by a processor, a request for at least a portion of memory in a computer system to be designated as RWORM memory. The processor further writes data to the RWORM memory. The processor further maintains the RWORM memory in a read-only state after the RWORM memory is written to. The processor further re-designates the RWORM memory to a read/write state in response to encountering a system reset.

公开(公告)号：US20200041547A1

公开(公告)日：2020-02-06

申请号：US16595635

申请日：2019-10-08

Applicant: Renesas Electronics Corporation

Inventor： Kazuki FUKUOKA ,  Toshifumi UEMURA ,  Yuko KITAJI ,  Yosuke OKAZAKI ,  Akira MURAYAMA

IPC: G01R19/165 ,  G01R31/28 ,  G06F1/28 ,  H03K5/133 ,  H03K3/03 ,  G06F1/24 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3193

Abstract: A semiconductor device, a semiconductor system, and a control method of a semiconductor device are capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

公开(公告)号：US10530642B1

公开(公告)日：2020-01-07

申请号：US15660707

申请日：2017-07-26

Applicant: Palantir Technologies Inc.

Inventor： Kyle Owens ,  Daniel Berkowitz ,  Samuel Bond

IPC: G06F15/177 ,  H04L12/24 ,  H04L29/08 ,  G06F1/24 ,  G06F9/445

Abstract: Aspects of the present disclosure relate to remote configuration of a computing machine. A deployment server receives a request specifying a software configuration and a hardware configuration for a computing machine. The deployment server identifies, out of a plurality of computing machines available for deployment, a specific computing machine meeting the hardware configuration. The deployment server configures the specific computing machine based on the software configuration. The deployment server provides an output indicating that the specific computing machine is configured according to the request.

公开(公告)号：US10476499B2

公开(公告)日：2019-11-12

申请号：US15951772

申请日：2018-04-12

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chin-Yuan Wei ,  Chih-Hsien Wang

IPC: H03L7/00 ,  H03K17/22 ,  G06F1/24 ,  H03F3/16 ,  H03K3/356 ,  H03F3/45

Abstract: A power-on reset (POR) circuit includes: a signal generator circuit for generating a first and a second signal according to an input voltage, and a comparator circuit. The comparator circuit, having a non-zero input offset, includes a first MOS transistor with a first conductive type and having a first conductive type gate and a first threshold voltage, and a second MOS transistor with a first conductive type and having a second conductive type gate and a second threshold voltage. The input offset relates to a difference between the first and the second threshold voltage. The first and the second signal control the first and the second MOS transistors respectively to generate a POR signal. When the input voltage exceeds a POR threshold which relates to a predetermined multiple or ratio of the input offset, the POR signal transits its state.

公开(公告)号：US10466752B2

公开(公告)日：2019-11-05

申请号：US14849796

申请日：2015-09-10

Applicant: CANON KABUSHIKI KAISHA

Inventor： Hiroshi Yamamizu

IPC: G06F11/14 ,  G06F1/24 ,  G06F1/26 ,  G03G15/00 ,  H04N1/00 ,  G06F1/3203

Abstract: An information processing apparatus which is capable of, when hang-up occurs, eliminating the hang-up state and restoring to a normal state without bothering a user. A first power supply unit supplies power to predetermined devices among a plurality of devices, and a second power supply unit supplies power to the plurality of devices. When startup is done with power being supplied to the predetermined devices, software is started by supplying power to all of the plurality of devices. When the second power supply unit is turned on during the startup, whether or not the software has been normally started is determined. When the software has not been normally started, the software is restarted by carrying out an off-on process in which the plurality of devices are reset, the second power supply unit is turned off, and then the second power supply unit is turned on again.

公开(公告)号：US10431029B2

公开(公告)日：2019-10-01

申请号：US15884635

申请日：2018-01-31

Applicant: Deutsche Post AG ,  Kobil Systems GmbH ,  Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Christian Carstens ,  Christoph Dautz ,  Jochen Jansen ,  Ramin Benz ,  Alexandra Dmitrienko ,  Stanislav Bulygin ,  Marcus Lippert

IPC: G07C9/00 ,  H04W56/00 ,  H04L29/06 ,  G06F1/12 ,  H04L9/08 ,  G06F1/24 ,  H04W12/08 ,  H04W4/80 ,  A47G29/14 ,  A47G29/16 ,  G07F17/12 ,  G06Q10/08 ,  H04L9/32 ,  H04L9/00 ,  E05B43/00 ,  E05B65/00 ,  E05B47/00 ,  E05B65/52 ,  E05C9/08 ,  E05C9/18 ,  H04L9/14 ,  H04L9/30 ,  G06F1/10 ,  G06F21/31 ,  H04L7/00 ,  G06F1/04 ,  H04L9/06

Abstract: Provided is a method for access control, performed by an access control apparatus, including obtaining access authorization information that is communicated to the access control apparatus having at least one access authorization parameter and first check information; using at least the communicated access authorization parameters, the communicated first check information and a second key from a key pair, which second key is stored in the access control apparatus, to perform a first check on whether the communicated first check information has been produced by performing cryptographic operations by means of access authorization parameters corresponding to the communicated access authorization parameters using at least one first key from the key pair, and deciding whether access can be granted, based on the first check delivers a positive result and it is established that at least one predefined set of the communicated access authorization parameters respectively provides access authorization.

公开(公告)号：US20190272176A1

公开(公告)日：2019-09-05

申请号：US15910831

申请日：2018-03-02

Applicant: Dell Products L.P.

Inventor： Jayanth Raghuram ,  Rui Shi ,  Ching-Lung Chao

IPC: G06F9/4401 ,  G06F1/24

Abstract: A chipset fuse programming system includes a chassis that houses a chipset with programmable fuses and a Basic Input/Output System (BIOS) that is coupled to the chipset. The BIOS includes a BIOS storage storing fuse configuration profiles. The BIOS determines a chipset type of the chipset and selects a first fuse configuration profile based on the chipset type. The BIOS then programs the programmable fuses included in the chipset using the first fuse configuration profile. A central processing system may be housed in the chassis and coupled to the BIOS, with the BIOS determining a central processing system type of the central processing system, and selecting the first fuse configuration profile based on a combination of the chipset type and the central processing system type.