公开(公告)号：US4901285A

公开(公告)日：1990-02-13

申请号：US316590

申请日：1989-02-27

申请人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

发明人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

IPC分类号： G11C17/12

CPC分类号： G11C17/126

摘要： An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.

摘要翻译： 一种具有多条行线的集成电路存储器; 多条选择线; 多个输出线; 多个存储单元; 每对存储器单元具有耦合到所述多条输出线中的选择一条输出线的公共输出和耦合到所述多条行线中的选择一条线的公共地址输入，其中所选择的所述一对存储器单元中的存储单元的模糊性 耦合到所述多行输入行中的选择一行和所述多条输出行中的选择一行由所耦合的所述多条选择行中的两个选定行选择。 还提供了响应于输入地址以启用多条行线中的选择行的第一解码器，以及响应于行线和输入地址的第二解码器，用于启用选择线中的选择线 其对应于具有启用行行的存储器单元对。

公开(公告)号：US4896300A

公开(公告)日：1990-01-23

申请号：US126258

申请日：1987-11-25

申请人： Yutaka Shinagawa ,  Shigeru Shimada

发明人： Yutaka Shinagawa ,  Shigeru Shimada

IPC分类号： G11C17/12 ,  G11C8/08 ,  G11C11/407 ,  G11C17/18

CPC分类号： G11C8/08

摘要： A semiconductor memory includes a word line driving circuit whose output terminal is coupled to one end of each word line of a memory array, and also an auxiliary driving circuit which drives the other end of the word line upon receiving a selection signal transmitted to the other end of this word line. The auxiliary driving circuit comprises a level detector circuit which is dynamically driven by a timing signal, and a driving element which is driven by an output of the level detector circuit to drive the other end of the word line. When the word line is to be reset, the output of the level detector circuit is set at a level which brings the driving element into an "off" state. The auxiliary driving circuit of this arrangement permits the other end of the word line to change to a selection level quickly and to be reset quickly.

公开(公告)号：US4821239A

公开(公告)日：1989-04-11

申请号：US89681

申请日：1987-08-25

申请人： Lavi A. Lev

发明人： Lavi A. Lev

IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C16/02 ,  G11C17/12 ,  G11C7/00

CPC分类号： G11C7/067 ,  G11C17/12

摘要： A programmable sense amplifier in accordance with the present invention includes an input multiplexer which receives a plurality of data input signals from the column lines of a ROM and provides a selected one of a data input signals as a data output signal based on control signals proviced to the input multiplexer. The voltage level of the data output signal corresponds to the number of 1's contained in the selected column line. A sensing stage receives the data output signal and amplifies it. The amplified signal is then provided to an XOR gate which either does or does not invert the amplified signal, based upon the state of the select node to which one of the XOR gate inputs is connected. The state of the select node is determined by a programmable internal multiplexer. The internal multiplexer comprises a number of FET switching transistors corresponding to the number of data input signals. Each of the switching transistors has one of its electrode areas commonly-connected to the select node. The other area of each switching transistor is selectively, i.e. programmably, connected either to the negative supply V.sub.SS or the positive supply V.sub.CC depending upon whether or not, respectively, a number of "1"s contained in the selected column line exceeds one-half the total number of row lines of the ROM, the 1s and 0s in the selected column line having been inverted if this is the case. Thus, the select mode will be appropriately charged or discharged because the XOR gate to produce the correct sense amplifier output.

公开(公告)号：US4811301A

公开(公告)日：1989-03-07

申请号：US43381

申请日：1987-04-28

申请人： Theodore W. Houston

发明人： Theodore W. Houston

IPC分类号： G11C17/12 ,  G11C7/00

CPC分类号： G11C17/126

摘要： A low-power, noise-resistant, read-only memory (10) is comprised of a plurality of array sections (14), each section (14) having a plurality of cell locations (70-86) arranged in rows (98) and columns (88-96). Each column (88-96) is provided with a virtual ground line (107-114). Bit lines (116-126) are shared between columns (88-96). In operation, the bit lines (116-126) and virtual ground lines (107-114) are pulled up to a high voltage state. Then, one selected virtual ground line (107-114) in each section (14) is pulled low to address a pair of cell locations (70, 72) in that section (14). No active pullup means are employed. The transmission of false data through a sneak path (550) is prevented by the actuation of disconnect circuitry (38) after allowing all valid data to be sensed.

摘要翻译： 低功率，耐噪声的只读存储器（10）由多个阵列部分（14）组成，每个部分（14）具有排成行（98）的多个单元位置（70-86） 和列（88-96）。 每列（88-96）设有虚拟接地线（107-114）。 位线（116-126）在列之间共享（88-96）。 在工作中，位线（116-126）和虚拟接地线（107-114）被拉高到高电压状态。 然后，将每个部分（14）中的一个选择的虚拟接地线（107-114）拉低，以寻址该部分（14）中的一对单元位置（70,72）。 没有采用有源上拉装置。 通过在允许检测到所有有效数据之后通过断开电路（38）的致动来防止通过潜行路径（550）发送假数据。

公开(公告)号：US4758994A

公开(公告)日：1988-07-19

申请号：US820286

申请日：1986-01-17

申请人： Rohit L. Bhuva

发明人： Rohit L. Bhuva

IPC分类号： G11C17/08 ,  G11C5/14 ,  G11C17/06 ,  G11C17/12 ,  G11C17/14 ,  G11C17/18 ,  G11C17/00

CPC分类号： G11C5/147 ,  G11C17/18

摘要： A programmable memory includes a voltage regulator (32) which is disposed between the supply voltage and the matrix supply line (10) for programmable memory cells. Each of the memory cells is comprised of a transistor (12) and a series fusible link (16). By maintaining a constant voltage on the matrix supply line (10), transients on the supply pin of a memory chip cannot cause spurious changes in the logic state of the memory cell resulting from parasitic capacitance (28).

摘要翻译： 可编程存储器包括电压调节器（32），其设置在用于可编程存储器单元的电源电压和矩阵电源线（10）之间。 每个存储单元由晶体管（12）和串联熔丝（16）构成。 通过在矩阵电源线（10）上保持恒定电压，存储器芯片的电源引脚上的瞬变不会由于寄生电容（28）而导致存储器单元的逻辑状态发生寄生变化。

公开(公告)号：US4719603A

公开(公告)日：1988-01-12

申请号：US852316

申请日：1986-04-15

申请人： Yutaka Shinagawa ,  Shigeru Shimada

发明人： Yutaka Shinagawa ,  Shigeru Shimada

IPC分类号： G11C17/12 ,  G11C8/08 ,  G11C11/407 ,  G11C17/18 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C8/08

摘要： A semiconductor memory includes a word line driving circuit whose output terminal is coupled to one end of each word line of a memory array, and also an auxiliary driving circuit which drives the other end of the word line upon receiving a selection signal transmitted to the other end of this word line. The auxiliary driving circuit comprises a level detector circuit which is dynamically driven by a timing signal, and a driving element which is driven by an output of the level detector circuit to drive the other end of the word line. When the word line is to be reset, the output of the level detector circuit is set at a level which brings the driving element into an "off" state. The auxiliary driving circuit of this arrangement permits the other end of the word line to change to a selection level quickly and to be reset quickly.

摘要翻译： 半导体存储器包括字线驱动电路，其输出端耦合到存储器阵列的每个字线的一端，以及辅助驱动电路，其在接收到发送到另一个的选择信号时驱动字线的另一端 这个字线的结尾。 辅助驱动电路包括由定时信号动态驱动的电平检测器电路和由电平检测器电路的输出驱动以驱动字线另一端的驱动元件。 当字线被复位时，电平检测器电路的输出被设置在使驱动元件处于“关闭”状态的水平。 这种布置的辅助驱动电路允许字线的另一端快速地改变到选择电平并被快速复位。

公开(公告)号：US4644501A

公开(公告)日：1987-02-17

申请号：US680125

申请日：1984-12-10

申请人： Masanori Nagasawa

发明人： Masanori Nagasawa

IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C7/14 ,  G11C11/41 ,  G11C16/06 ,  G11C17/12 ,  G11C17/18 ,  G11C7/00

CPC分类号： G11C17/12 ,  G11C7/12 ,  G11C7/14

摘要： A semiconductor memory device, such as a mask ROM device, wherein precharge time is controlled by the chargeup level of a dummy bit line. The semiconductor memory device comprises a gate circuit for selecting a desired bit line, a dummy bit line having a chargeup characteristic equivalent to that of each of the bit lines, a dummy bit line chargeup circuit for charging the dummy bit line, and a chargeup circuit for charging up the selected bit line from the time the bit line is selected to the time the chargeup of the dummy bit line is finished, on the basis of the chargeup level of the dummy bit line, thereby enabling chargeup of the selected bit line for the necessary period without the intervention of excess time.

摘要翻译： 诸如掩模ROM器件的半导体存储器件，其中预充电时间由虚拟位线的电荷电平来控制。 半导体存储器件包括用于选择所需位线的栅极电路，具有与每个位线相同的电荷特性的虚拟位线，用于对虚拟位线充电的虚拟位线电荷电路和充电电路 用于根据虚拟位线的电荷电平从选择位线的时间到虚拟位线的充电时间对所选择的位线进行充电，从而使所选位线的电荷为 必要的时期没有超时的干预。

公开(公告)号：US4571708A

公开(公告)日：1986-02-18

申请号：US686330

申请日：1984-12-26

申请人： Harold L. Davis

发明人： Harold L. Davis

IPC分类号： G11C17/12 ,  G11C17/18 ,  H03K17/693 ,  G11C11/40

CPC分类号： G11C17/126

摘要： A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors on the bit lines, the pass transistor gates being controlled not by an inverted column decode line, but by the column line itself, thus reducing the capacative load on the column decoder and saving space.

摘要翻译： 用于选择CMOS ROM中的列线并且用于建立一对位线和相应数据线之间的连接的数据选择电路使用列线上的单个NMOS下拉晶体管和一对P沟道传输晶体管 位线，传输晶体管栅极不是由反相列解码线控制，而是由列线本身控制，从而降低列解码器上的电容负载并节省空间。

公开(公告)号：US4494187A

公开(公告)日：1985-01-15

申请号：US350960

申请日：1982-02-22

申请人： Richard D. Simpson

发明人： Richard D. Simpson

IPC分类号： G06F9/32 ,  G06F12/06 ,  G11C17/12 ,  G06F13/00

CPC分类号： G06F12/0607 ,  G06F9/32 ,  G11C17/12

摘要： A system for real-time digital processing employs a single-chip microcomputer device having a high-speed on-chip program ROM and a separate data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program ROM has a low-level precharge circuit with feedback to improve speed or access time.

摘要翻译： 一种用于实时数字处理的系统采用具有高速片上程序ROM和独立数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。 片上程序ROM具有具有反馈的低电平预充电电路，以提高速度或访问时间。

公开(公告)号：US4489399A

公开(公告)日：1984-12-18

申请号：US354500

申请日：1982-03-03

申请人： Yasuo Suzuki ,  Hiroshi Hirao

发明人： Yasuo Suzuki ,  Hiroshi Hirao

IPC分类号： G11C17/00 ,  G11C11/417 ,  G11C11/419 ,  G11C16/08 ,  G11C16/24 ,  G11C17/12 ,  G11C17/18 ,  G11C7/00

CPC分类号： G11C17/12 ,  G11C16/08 ,  G11C16/24 ,  G11C17/18

摘要： A read-only memory device comprises a plurality of groups of bit lines (BL.sub.0, BL.sub.1, . . . , BL.sub.63). One bit line within each group is selected by first column address decoders (4-1) and one group is selected by second column address decoders (8-0.about.8-3). One load element (Q.sub.L0, Q.sub.L1, Q.sub.L2, Q.sub.L3) is provided in each second column address decoder to pull up the potentials of the bit lines.

摘要翻译： 只读存储器件包括多组位线（BL0，BL1，...，BL63）。 每组中的一个位线由第一列地址解码器（4-1）选择，一组由第二列地址解码器（8-0差分8-3）选择。 在每个第二列地址解码器中提供一个负载元件（QL0，QL1，QL2，QL3）以提升位线的电位。