A semiconductor memory device, such as a mask ROM device, wherein precharge time is controlled by the chargeup level of a dummy bit line. The semiconductor memory device comprises a gate circuit for selecting a desired bit line, a dummy bit line having a chargeup characteristic equivalent to that of each of the bit lines, a dummy bit line chargeup circuit for charging the dummy bit line, and a chargeup circuit for charging up the selected bit line from the time the bit line is selected to the time the chargeup of the dummy bit line is finished, on the basis of the chargeup level of the dummy bit line, thereby enabling chargeup of the selected bit line for the necessary period without the intervention of excess time.