公开(公告)号：US09722537B2

公开(公告)日：2017-08-01

申请号：US14831784

申请日：2015-08-20

Applicant: Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03B1/00 ,  H03K3/015 ,  H03L7/093 ,  H03B5/12 ,  G04F10/00 ,  H03L7/08 ,  H03M1/00 ,  H03M1/20 ,  H03L7/089 ,  H03L7/197 ,  H03K3/03

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

公开(公告)号：US09331709B2

公开(公告)日：2016-05-03

申请号：US14162572

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/20 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

公开(公告)号：US20160056799A1

公开(公告)日：2016-02-25

申请号：US14831119

申请日：2015-08-20

Applicant: Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03K3/015 ,  H03B1/00

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

公开(公告)号：US09231611B2

公开(公告)日：2016-01-05

申请号：US14162567

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/06 ,  H03M1/20 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。

公开(公告)号：US20150244387A1

公开(公告)日：2015-08-27

申请号：US14544851

申请日：2015-02-25

Applicant: Elta Systems Ltd.

Inventor： Baruch Fleishman

IPC: H03M1/20

CPC classification number: H03M1/201 ,  H04B1/0007 ,  H04B7/086

Abstract: A system and method for enhancing a dynamic range of a beamforming multi-channel digital receiver are described. The receiver comprises a plurality of receiving channels, each including an analog-to-digital converter configured for converting an analog input signal generated by antenna elements into a digital signal. A “spatial” dither signal is used to decorrelate the quantization noise of the analog-to-digital converters. A dither signal is generated and split into a predetermined number of coherent dithering signals. The method includes providing predetermined time delays to the coherent dithering signals, and adding the delayed coherent dithering signals to the input signals in each receiving channel, correspondingly, thereby creating a dither signal equivalent to a signal arriving from a certain specific direction out-of-field-of-view of the antenna array. Removing of the dither signal based on the direction of arrival, is implemented during beamforming signal processing, thus enhancing the dynamic range of electromagnetic signals arriving within a field-of-view of the antenna array.

Abstract translation: 描述了用于增强波束成形多通道数字接收机的动态范围的系统和方法。 接收机包括多个接收通道，每个接收通道包括被配置用于将由天线元件产生的模拟输入信号转换为数字信号的模拟 - 数字转换器。 “空间”抖动信号用于去相关模拟数字转换器的量化噪声。 产生抖动信号并将其分成预定数量的相干抖动信号。 该方法包括向相干抖动信号提供预定的时间延迟，并相应地将延迟的相干抖动信号加到每个接收信道中的输入信号上，从而产生相当于从某个特定方向到达的信号的抖动信号， 天线阵列的视场。 在波束形成信号处理期间实现基于到达方向去除抖动信号，从而增强到达天线阵列的视场内的电磁信号的动态范围。

公开(公告)号：US20140333461A1

公开(公告)日：2014-11-13

申请号：US14445682

申请日：2014-07-29

Applicant: Renesas Electronics Corporation

Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

IPC: H03M3/00 ,  H03M1/20

CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

公开(公告)号：US08836564B2

公开(公告)日：2014-09-16

申请号：US13814205

申请日：2012-03-21

Applicant: Taiji Akizuki ,  Suguru Fujita

Inventor： Taiji Akizuki ,  Suguru Fujita

IPC: H03M1/12 ,  H03M1/20

CPC classification number: H03M1/20 ,  H03M1/201

Abstract: An A/D conversion device generates a control clock signal having a cycle that is an integral multiple of a cycle of a reference clock signal. A shift voltage is generated which varies every cycle of the reference clock signal while the cycle of the control clock signal is taken as one cycle. An analog signal is offset by the shift voltage. The offset analog signal is converted to a digital signal every cycle of the reference clock signal. Outputs from the A/D converter are averaged every cycle of the control clock signal.

Abstract translation: A / D转换装置产生具有作为参考时钟信号的周期的整数倍的周期的控制时钟信号。 产生一个转换电压，当控制时钟信号的周期作为一个周期时，基准时钟信号的每个周期都会改变。 模拟信号被移位电压偏移。 偏移模拟信号在参考时钟信号的每个周期被转换成数字信号。 来自A / D转换器的输出在控制时钟信号的每个周期进行平均。

公开(公告)号：US08810443B2

公开(公告)日：2014-08-19

申请号：US13553092

申请日：2012-07-19

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/20

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。

公开(公告)号：US08711027B1

公开(公告)日：2014-04-29

申请号：US13681371

申请日：2012-11-19

Applicant: Western Digital Technologies, Inc.

Inventor： George J. Bennett

IPC: H03M1/50

CPC classification number: H03M1/201 ,  H03L7/0891 ,  H03L7/093 ,  H03M1/12 ,  H03M1/504

Abstract: An analog-to-digital converter is disclosed comprising a resonant oscillator comprising an input operable to receive an analog input signal and an output operable to output an oscillating signal. A DC offset detector detects a DC offset in the oscillating signal caused by the analog input signal, wherein the DC offset is converted into a digital output signal representing the analog input signal.

Abstract translation: 公开了一种模拟 - 数字转换器，其包括谐振振荡器，其包括可操作以接收模拟输入信号的输入和可操作以输出振荡信号的输出。 DC偏移检测器检测由模拟输入信号引起的振荡信号中的DC偏移，其中DC偏移被转换成表示模拟输入信号的数字输出信号。

公开(公告)号：US20130331052A1

公开(公告)日：2013-12-12

申请号：US13969549

申请日：2013-08-17

Applicant: Broadcom Corporation

Inventor： Henrik Tholstrup Jensen ,  Jianhua Gan ,  Seema Anand ,  Aminghasem Safarian

IPC: H03M1/20

CPC classification number: H03M1/201 ,  H03M3/332 ,  H03M3/396 ,  H03M3/406 ,  H03M3/456

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency hands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract translation: 技术和设备在两个或多个信号频率或频带上提供模数转换，并可用于在各种电路中构建多模式模数转换器，包括用于无线通信和无线电广播环境的接收机和收发器。 可以配置基于所述技术的可调节模数转换器，以调整电路参数，以适应不同信号频率或频段的不同输入信号的技术规格，例如无线电中的FM，HD-无线电和DAB无线电信号 接收机应用。