公开(公告)号：US08502594B2

公开(公告)日：2013-08-06

申请号：US12628945

申请日：2009-12-01

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03K5/00 ,  H03K17/00 ,  H03K17/04 ,  H03K17/687 ,  H02M3/07

CPC classification number: H03K17/102 ,  H03K17/063 ,  H03K17/162 ,  H03K2217/0054

Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.

Abstract translation: 描述了开关电路，其中要控制的开关由其源极端子连接在一起并且其栅极端子连接在一起的两个NMOS晶体管形成。 它们的漏极端子是开关的输入和输出端子。 驱动电路控制由锁存电路和电容器形成的自举电路。 当开关处于断开状态时，驱动电路将电容器连接到充电电压源，用于将电容器充电至自举电压，并在锁存电路两端施加非零电压。 当驱动电路被控制以接通开关时，驱动电路将电容器与充电电压源断开，并且锁存电路变得导通并且有效地将电容器跨过开关的栅极和源极端子连接，使其接通 自举电压。 电容器两端的自举电压将锁存电路保持在锁定的导通状态。

公开(公告)号：US06573790B2

公开(公告)日：2003-06-03

申请号：US09759618

申请日：2001-01-12

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03F136

CPC classification number: H03F1/3258 ,  H03F1/083 ,  H03F1/3211 ,  H03F1/483 ,  H03F3/45197 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/331 ,  H03F2200/39

Abstract: An operational amplifier (opamp) [74] coupled in a negative-feedback configuration [82] [84] comprising a driving opamp [76]; a linear controller [78]; and a mechanism [80] controlling the driving opamp's [76] offset. A voltage signal Vin provided by the feedback network [82][84] characterizes all errors caused by the driving opamp [76]. The controller [78] monitors this voltage and minimizes the signal-band spectral components thereof by inducing an offset in the driving opamp [76]. The offset control mechanism [80] has approximately constant gain and only little phase delay in the signal band. The controller [78] may be a linear high-order Chebychev filter providing substantial gain in a wide frequency range, thereby efficiently suppressing all signal-band errors, including noise, harmonic distortion, and slew-rate errors, caused by the driving opamp [76]. The controller's [78] frequency response can be designed essentially independently of the feedback network's [82][84] feedback factor. The operational amplifier [74] is a general-purpose circuit. Important applications include video amplifiers and current-to-voltage conversion for asynchronous-digital-subscriber-line (ADSL) moderns.

Abstract translation: 耦合在负反馈配置[82] [84]中的运算放大器（运算放大器）[74]包括驱动运算放大器[76] 线性控制器[78]; 以及控制驾驶员的[76]偏移的机构[80]。 由反馈网络[82] [84]提供的电压信号Vin表征了由驾驶操纵器引起的所有错误[76]。 控制器[78]通过在驱动运算放大器中引起偏移来监视该电压并使其信号频带频谱分量最小化[76]。 偏移控制机构[80]具有大致恒定的增益，并且在信号频带中仅具有很小的相位延迟。 控制器[78]可以是在宽频率范围内提供实质增益的线性高阶切比雪夫滤波器，从而有效地抑制由驱动运算放大器引起的所有信号带误差，包括噪声，谐波失真和转换速率误差[ 76]。 控制器的[78]频率响应可以基本上独立于反馈网络[82] [84]反馈因子进行设计。运算放大器[74]是通用电路。 重要的应用包括视频放大器和用于异步数字用户线（ADSL）现代的电流 - 电压转换。

公开(公告)号：US5982317A

公开(公告)日：1999-11-09

申请号：US61671

申请日：1998-04-16

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/08 ,  H03M3/02 ,  H03M3/04 ,  H03M3/00

CPC classification number: H03M1/067 ,  H03M1/68 ,  H03M1/74 ,  H03M3/502

Abstract: A error-shaping digital-to-analog (D/A) converter system [100], consisting of a separator [102], a set of D/A converters [104] [108], a set of optional analog filters [106] [108], a summation device [112], and an optional analog filter [114]. The separator [102] separates the digital input signal into a set of low-resolution signals of which only one has significant power in the system's signal band. These signals are D/A converted by mismatch-shaping D/A converters [104] [108], in some embodiments filtered by analog filters [106] [108], and then added by the summing device [112]. Imperfections of the employed D/A converters [104] [108] will only cause very small errors in the signal band, such errors being essentially uncorrelated to the digital input signal. The D/A converter system is comparable to a scaled-element D/A converter in which the distortion is transformed into a noise component having very little power in the signal band.

Abstract translation: 由分离器[102]，一组D / A转换器[104] [108]，一组可选的模拟滤波器[106]组成的数模转换器（D / A）转换器系统[100] [108]，求和装置[112]和可选的模拟滤波器[114]。 分离器[102]将数字输入信号分离成一组低分辨率信号，其中仅一个信号在系统的信号频带中具有有效功率。 这些信号是由失配整形D / A转换器[104] [108]转换的D / A，在一些实施例中，由模拟滤波器[106] [108]滤波，然后由求和装置[112]相加。 使用的D / A转换器[104] [108]的缺陷将仅在信号频带中引起非常小的误差，这种误差基本上与数字输入信号不相关。 D / A转换器系统与其中将失真转换成在信号频带中具有非常小的功率的噪声分量的缩放元件D / A转换器相当。

公开(公告)号：US20120026027A1

公开(公告)日：2012-02-02

申请号：US12844727

申请日：2010-07-27

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/38 ,  H03K5/00 ,  H03M1/12

CPC classification number: H03M1/466

Abstract: In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated.

Abstract translation: 在A / D转换器中，电容器和转换开关之间使用隔离开关。 转换开关是用于在A / D转换过程期间将二进制加权电容器的板选择性地耦合到Vref或0伏的那些开关。 在采样输入电压信号期间，隔离开关被打开以将转换开关与电容器底板的可能输入电压的宽范围隔离开来。 因此，转换开关两端的电压基本上限制在Vref。 因此，转换开关可以是非常快速的低压开关。 在对输入电压进行采样之后，当采样的输入电压被锁定时，转换开关正常工作，选择性地将电容器板连接到Vref或0伏，以连续逼近输入电压，从而表示采样输入电压的数字代码为 生成。

公开(公告)号：US07961132B1

公开(公告)日：2011-06-14

申请号：US12699794

申请日：2010-02-03

Applicant: Raymond T. Perry ,  Jesper Steensgaard-Madsen

Inventor： Raymond T. Perry ,  Jesper Steensgaard-Madsen

IPC: H03M1/12

CPC classification number: H03M1/0607 ,  H03M1/466 ,  H03M1/468

Abstract: In one embodiment, an A/D converter samples an analog input signal voltage by applying the input signal to a first capacitor terminal, while a second capacitor terminal is connected to ground via an NMOS sampling switch, to charge the capacitor to the input signal voltage. During an analog-to-digital conversion process, the second capacitor terminal may swing in a voltage range that extends below ground. A controller circuit provides bias voltage signals to a gate terminal and to a p-well of the NMOS sampling switch, to selectively turn the sampling switch on and off. In a first step of a multi-step sampling process, the controller very quickly discharges the gate terminal to ground to isolate a quantity of charge on the second capacitor plate. In a subsequent step of the sampling process, the controller circuit applies a negative voltage to the gate terminal and p-well to ensure that the quantity of change is substantially preserved during the ensuing analog-to-digital conversion process.

Abstract translation: 在一个实施例中，A / D转换器通过将输入信号施加到第一电容器端子来对模拟输入信号电压进行采样，而第二电容器端子经由NMOS采样开关连接到地，以将电容器充电到输入信号电压 。 在模数转换处理期间，第二电容器端子可以在低于地面的电压范围内摆动。 控制器电路向NMOS采样开关的栅极端子和p阱提供偏置电压信号，以选择性地打开和关闭采样开关。 在多步采样过程的第一步中，控制器非常快速地将栅极端子放电到地以隔离第二电容器板上的电荷量。 在采样过程的后续步骤中，控制器电路向栅极端子和p阱施加负电压，以确保在随后的模数转换过程期间基本上保持变化量。

公开(公告)号：US20100164597A1

公开(公告)日：2010-07-01

申请号：US12628945

申请日：2009-12-01

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03K17/16

CPC classification number: H03K17/102 ,  H03K17/063 ,  H03K17/162 ,  H03K2217/0054

Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.

Abstract translation: 描述了开关电路，其中要控制的开关由其源极端子连接在一起并且其栅极端子连接在一起的两个NMOS晶体管形成。 它们的漏极端子是开关的输入和输出端子。 驱动电路控制由锁存电路和电容器形成的自举电路。 当开关处于断开状态时，驱动电路将电容器连接到充电电压源，用于将电容器充电至自举电压，并在锁存电路两端施加非零电压。 当驱动电路被控制以接通开关时，驱动电路将电容器与充电电压源断开，并且锁存电路变得导通并且有效地将电容器跨过开关的栅极和源极端子连接，使其接通 自举电压。 电容器两端的自举电压将锁存电路保持在锁定的导通状态。

公开(公告)号：US06556158B2

公开(公告)日：2003-04-29

申请号：US09694063

申请日：2001-03-05

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03M112

CPC classification number: H03M3/416 ,  H03M1/145

Abstract: An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero. An analog compensation signal, m0, which is described by a well-controlled relationship to the residue signal, r0, is extracted from the filter [158]. Ideally, the closed-loop signal transfer function from g to m0 will be zero, or at least small in the signal band. A second quantizer [160] converts the analog compensation signal, m0, into a second digital signal, dm0(k). The two digital signals, d0(k) and dm0(k), are filtered individually and then added to form the overall output signal, dg(k). The second digital filter [164] has a low signal-band gain, which implies that the sensitivity to signal-band errors caused by the second quantizer [160] will be low. The output signal, dg(k), is a highly-accurate high-resolution representation of the input signal, g. Circuit imperfections, such as mismatch, gain errors, and nonlinearities, will cause only noise-like errors having a very low spectral power density in the signal band. The invention facilitates the implementation of uncalibrated highly-linear high-resolution wide-bandwidth A/D converters [50D], e.g., for use in digital communication systems, such as xDSL modems and other demanding consumer-market products for which low cost is of the essence.

公开(公告)号：US06215348B1

公开(公告)日：2001-04-10

申请号：US09163533

申请日：1998-09-30

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03K1716

CPC classification number: H03K17/063 ,  H03K2217/0018

Abstract: A low-voltage constant-impedance analog switch based on a single MOSFET [328] as the main switching element. The constant-impedance on-state operation is obtained by connecting a charged capacitor [326] between the gate and source terminals of the MOSFET [328]. The switch can be compensated for the body effect, which may be necessary to obtain the required level of linearity. Low-voltage operation is made feasible by employing an internal feedback loop that locks in the switch's on-state. The switch can be implemented in a single-well CMOS bulk technology, and it can operate at supply-voltage differences that are only slightly higher than the technology's threshold voltage.

Abstract translation: 基于单个MOSFET [328]作为主要开关元件的低压恒定阻抗模拟开关。 通过连接MOSFET的栅极和源极端子之间的充电电容器[326]获得恒定阻抗导通状态操作。 该开关可以补偿身体效应，这可能是获得所需的线性水平所必需的。 通过采用锁定开关导通状态的内部反馈回路，可以实现低压运行。 该开关可以在单阱CMOS体积技术中实现，并且它可以在仅比技术的阈值电压略高的电源电压差下工作。

公开(公告)号：US08319673B2

公开(公告)日：2012-11-27

申请号：US12861696

申请日：2010-08-23

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/00

CPC classification number: H03M1/18

Abstract: An embodiment of an analog-to-digital converter system is described wherein an analog voltage signal Vin(t) is provided by an input amplifier. The analog signal Vin(t) has a predetermined full-scale range that is less wide than a reference voltage (Vref) range used by a downstream ADC to derive a first digital (numerical) representation D1(k) of a sampled value Vin(k) of the analog signal Vin(t). The first digital representation has N bits. A digital circuit then converts the N-bit D1(k) code to a second numerical representation D2(k) of the sampled analog voltage Vin(k) with respect to the full-scale range of the ADC system. The D2(k) code has P bits of resolution, which may be less than N bits. The P-bit D2(k) code representing Vin(k) is the output of the ADC system. Therefore, the width of the reference voltage range applied to the ADC is greater than the width of the system's full-scale range at the output of the system.

Abstract translation: 描述了模数转换器系统的实施例，其中模拟电压信号Vin（t）由输入放大器提供。 模拟信号Vin（t）具有比下游ADC使用的参考电压（Vref）范围宽的预定满量程范围，以导出采样值Vin的第一数字（数值）表示D1（k） k）的模拟信号Vin（t）。 第一个数字表示有N位。 然后，数字电路相对于ADC系统的满量程范围将N位D1（k）码转换为采样模拟电压Vin（k）的第二数值表示D2（k）。 D2（k）代码具有分辨率的P位，其可以小于N位。 表示Vin（k）的P位D2（k）代码是ADC系统的输出。 因此，施加到ADC的参考电压范围的宽度大于系统输出端系统满量程范围的宽度。

公开(公告)号：US08130133B2

公开(公告)日：2012-03-06

申请号：US12844727

申请日：2010-07-27

Applicant: Jesper Steensgaard-Madsen

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/12

CPC classification number: H03M1/466

Abstract: In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated.

Abstract translation: 在A / D转换器中，电容器和转换开关之间使用隔离开关。 转换开关是用于在A / D转换过程期间将二进制加权电容器的板选择性地耦合到Vref或0伏的那些开关。 在采样输入电压信号期间，隔离开关被打开以将转换开关与电容器底板的可能输入电压的宽范围隔离开来。 因此，转换开关两端的电压基本上限制在Vref。 因此，转换开关可以是非常快速的低压开关。 在对输入电压进行采样之后，当采样的输入电压被锁定时，转换开关正常工作，选择性地将电容器板连接到Vref或0伏，以连续逼近输入电压，由此表示采样输入电压的数字代码为 生成。