公开(公告)号：US20100191934A1

公开(公告)日：2010-07-29

申请号：US12726694

申请日：2010-03-18

Applicant: Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

Inventor： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30 ,  G06F15/76 ,  G06F9/06

CPC classification number: G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract translation: 这里公开了采用通用寄存器方法的微计算机MCU。 微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过 采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US20100161950A1

公开(公告)日：2010-06-24

申请号：US12344151

申请日：2008-12-24

Applicant: Paul Caprioli ,  Peter B. Kessler ,  Christopher A. Vick

Inventor： Paul Caprioli ,  Peter B. Kessler ,  Christopher A. Vick

IPC: G06F9/30

CPC classification number: G06F9/322 ,  G06F9/324

Abstract: Apparatus and methods are disclosed for a computation processor that can execute a semi-absolute branch instruction, as well as methods of operation and of generating the semi-absolute branch instruction.

Abstract translation: 公开了一种可以执行半绝对分支指令的计算处理器以及操作方法和生成半绝对分支指令的装置和方法。

公开(公告)号：US20080313446A1

公开(公告)日：2008-12-18

申请号：US12195738

申请日：2008-08-21

Applicant: Megumi YOKOI ,  Masaki Ukai ,  Takashi Suzuki

Inventor： Megumi YOKOI ,  Masaki Ukai ,  Takashi Suzuki

IPC: G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3844

Abstract: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.

Abstract translation: 地址控制部分包括编码部分，用于生成通过从包括在指令地址中的预定高阶和低位比特部分压缩预定高阶比特部分而产生的高阶地址信息;以及恢复部分， 从高阶地址信息命令位部分。 分支指令预测部分包括历史存储器部分，该历史存储器部分存储与从高位比特确定的多个存储位置中的任一个存储处理的分支指令相对应的高位比特部分和低位比特部分 部分和低位比特部分对应于处理的分支指令的分支地址。

公开(公告)号：US20080209189A1

公开(公告)日：2008-08-28

申请号：US12071586

申请日：2008-02-22

Applicant: Yasuhiro Yamazaki

Inventor： Yasuhiro Yamazaki

IPC: G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3017 ,  G06F9/324 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/3844

Abstract: The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information indicating that the input instruction is a conditional branch instruction and instruction type information indicating a type of the conditional branch instruction when the input instruction is a conditional branch instruction, and writing the input instruction, from which the operation code is deleted, the conditional branch instruction information and the instruction type information to the instruction cache memory, and a history information writing unit writing history information indicating whether or not the conditional branch instruction was branched, as a result of executing the conditional branch instruction stored in the instruction cache memory, to an area in the instruction cache memory, where the operation code of the conditional branch instruction is deleted.

Abstract translation: 本发明提供了一种信息处理装置，其具有对输入指令中的操作码进行解码的预解码器，生成指示输入指令是条件转移指令的条件转移指令信息和指示条件转移指令的类型的指令类型信息， 指令是条件分支指令，并且将指定了运算代码的输入指令从条形分支指令信息和指令类型信息写入到指令高速缓冲存储器，以及历史信息写入部，写入表示是否进行历史信息 作为执行存储在指令高速缓存存储器中的条件转移指令的结果，条件转移指令被分支到指令高速缓存存储器中的区域，在该区域中，条件转移指令的操作代码被删除。

公开(公告)号：US07386709B2

公开(公告)日：2008-06-10

申请号：US10755449

申请日：2004-01-13

Applicant: Vladimir Vasekin

Inventor： Vladimir Vasekin

IPC: G06F9/40

CPC classification number: G06F9/3802 ,  G06F9/30054 ,  G06F9/324 ,  G06F9/3836

Abstract: A data processing apparatus is provided with an execute block instruction EMB which specifies a memory location of a block of program instructions to be executed as well as the length of that block of program instructions. When the end of that block of program instructions has been reached as tracked in response to the specified length value, a return to the main program flow is triggered. The instruction decoder can include a block counter register to keep track of the position within the block of program instructions being called. The block of program instructions are fetched by a prefetch unit into the instruction pipeline following the execute block instruction and are treated as having a program counter value corresponding to the execute block instruction whilst the block counter value keeps track of their separate positions within the block of program instructions.

Abstract translation: 数据处理装置具有执行块指令EMB，该指令指定要执行的程序指令块的存储器位置以及该程序指令块的长度。 当响应指定的长度值跟踪程序指令块的结束时，触发主程序流的返回。 指令解码器可以包括块计数器寄存器以跟踪被调用的程序指令块内的位置。 程序指令块由预取单元读取到执行块指令之后的指令流水线中，并且被视为具有与执行块指令相对应的程序计数器值，而块计数器值跟踪它们在该块内的单独位置 程序说明。

公开(公告)号：US07120779B2

公开(公告)日：2006-10-10

申请号：US10765092

申请日：2004-01-28

Applicant: David James Seal

Inventor： David James Seal

IPC: G06F12/06

CPC classification number: G06F9/342 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/322 ,  G06F9/324

Abstract: A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction encoding whilst maintaining backwards compatibility with that legacy encoding.

Abstract translation: 提供数据处理系统2，其支持地址偏移生成指令，其使用传统指令编码中的先前冗余位来编码地址偏移值的位，同时保持与该遗留编码的向后兼容性。

公开(公告)号：US07010665B1

公开(公告)日：2006-03-07

申请号：US10185513

申请日：2002-06-27

Applicant: Bret L. Toll ,  Michael J. St. Clair ,  John Allan Miller ,  Hitesh Ahuja

Inventor： Bret L. Toll ,  Michael J. St. Clair ,  John Allan Miller ,  Hitesh Ahuja

IPC: G06F12/02

CPC classification number: G06F9/322 ,  G06F9/30003 ,  G06F9/30054 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/324 ,  G06F9/342 ,  G06F9/3557 ,  G06F9/383

Abstract: A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

公开(公告)号：US20060031661A1

公开(公告)日：2006-02-09

申请号：US11245357

申请日：2005-10-07

Applicant: Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

Inventor： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC: G06F9/40

CPC classification number: G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

Abstract: When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract translation: 当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US06996700B2

公开(公告)日：2006-02-07

申请号：US10011807

申请日：2001-12-11

Applicant: Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

Inventor： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC: G06F9/32

CPC classification number: G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

公开(公告)号：US06948053B2

公开(公告)日：2005-09-20

申请号：US10082144

申请日：2002-02-25

Applicant: Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

Inventor： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

IPC: G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/322 ,  G06F9/324 ,  G06F9/3804

Abstract: A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n−1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n−1 lower order bits of the branch target address to form the complete branch target address.

Abstract translation: 一种用于计算分支目标地址的方法和系统。 在从存储器取出分支指令时，可以在将转移指令存储在指令高速缓存中之前将分支目标地址的n-1个较低位进行预先计算并存储在转移指令中。 在从指令高速缓存中检索分支指令时，可以使用分支指令中存储的符号位和进位位来恢复分支目标地址的高位。 符号位和进位位可用于选择分支目标地址的三个可能的高位位组合之一。 然后可以将所选择的高位比特值组合附加到分支目标地址的n-1个较低位，以形成完整的分支目标地址。