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    WIRING SUBSTRATE AND PROBE CARD
    3.
    发明申请
    WIRING SUBSTRATE AND PROBE CARD 有权
    接线基板和探头卡

    公开(公告)号：US20100327897A1

    公开(公告)日：2010-12-30

    申请号：US12735929

    申请日：2009-02-26

    申请人： Toshio Kazama ,  Hiroshi Nakayama ,  Shinya Miyaji ,  Kohei Suzuki

    发明人： Toshio Kazama ,  Hiroshi Nakayama ,  Shinya Miyaji ,  Kohei Suzuki

    IPC分类号： G01R1/073 ,  G01R31/26 ,  H05K1/00

    CPC分类号： G01R1/07378 ,  G01R31/2889 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/068

    摘要： A wiring substrate that allows wiring at a fine pitch and has a coefficient of thermal expansion close to the coefficient of thermal expansion of silicone, and a probe card that includes the wiring substrate are provided. To this end, there are provided a wiring substrate that includes a ceramic substrate having a coefficient of thermal expansion of 3×10−6 to 5×10−6/° C. and one or more thin-film wiring sheets stacked on one surface of the ceramic substrate, and a probe head on which a plurality of conductive proves are arranged in accordance with wiring on the thin-film wiring sheet, which holds individual probes while preventing the probes from coming off and allowing both ends of each probe to be exposed, and which is stacked on the wiring substrate while one end of each probe is brought into contact with the thin-film wiring sheet.

    摘要翻译： 提供允许以细间距布线并且具有接近硅树脂的热膨胀系数的热膨胀系数的布线基板和包括布线基板的探针卡。 为此，提供一种布线基板，其包括具有3×10-6〜5×10-6 /℃的热膨胀系数的陶瓷基板和在一个面上堆叠的一个以上的薄膜布线片 的陶瓷基板，以及探针头，根据薄膜布线片上的布线布置有多个导电证明物，该探针头保持各个探针，同时防止探针脱落并且允许每个探针的两端为 暴露，并且在每个探针的一端与薄膜布线片接触的同时在布线基板上层叠。

    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
    5.
    发明申请
    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 审中-公开
    处理器使用较少的硬件和指令转换设备减少指令类型的数量

    公开(公告)号：US20050091478A1

    公开(公告)日：2005-04-28

    申请号：US10617506

    申请日：2003-07-11

    申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F9/00

    CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

    摘要： A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.

    摘要翻译： 解码并执行指令序列的处理器包括：状态保持单元，用于当执行预定指令时，保持所述预定指令的执行结果的更新状态; 获取单元，用于获得指令序列，所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合，其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥， 第二条件指令，其具有与第一条件指令相同的操作码，指令集不被分配第二条件指令，以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元，用于逐个地解码所获得的指令序列中的每个指令; 判断单元，用于当解码单元解码第一条件指令时，判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元，用于仅当判断单元的判断结果为肯定时，执行由解码单元解码的第一条件指令中由操作码指定的操作。

    Debugger apparatus and debugging method
    6.
    发明申请
    Debugger apparatus and debugging method 审中-公开
    调试器和调试方法

    公开(公告)号：US20050033542A1

    公开(公告)日：2005-02-10

    申请号：US10899101

    申请日：2004-07-27

    申请人： Toru Morikawa ,  Kazuhide Watanabe ,  Shinya Miyaji

    发明人： Toru Morikawa ,  Kazuhide Watanabe ,  Shinya Miyaji

    IPC分类号： G06F11/36 ,  G06F13/00 ,  G06F19/00

    CPC分类号： G06F11/3636 ,  G06F11/3652

    摘要： A debugger apparatus according to the present embodiment comprises a host, CPU, a plurality of E-memory units (emulation memory units) for storing instructions, and an execution supervision unit. The host traces the instructions to be stored in the E-memory units and transfers the tracing result in the form of an instruction sequence. The execution supervision unit is connected to the CPU, E-memory units, and host. The execution supervision unit individually writes the instruction sequences transferred from the host in the plurality of E-memory units, reads an instruction sequence from one of the plurality of E-memory units in accordance with an instruction address of the CPU to thereby transfer the instruction sequence to the CPU, and outputs an instruction rewriting order to the host when the instruction address of the CPU is irrelevant.

    摘要翻译： 根据本实施例的调试器装置包括主机，CPU，用于存储指令的多个E存储器单元（仿真存储器单元）和执行监视单元。 主机跟踪要存储在E-memory单元中的指令，并以指令序列的形式传送跟踪结果。 执行监视单元连接到CPU，电子存储单元和主机。 执行监视单元将从主机传送的指令序列分别写入多个E存储单元中，根据CPU的指令地址从多个E存储器单元之一读取指令序列，从而传送指令 到CPU的序列，并且当CPU的指令地址不相关时，向主机输出指令重写顺序。

    Apparatus and method for processing data with a plurality of flag groups
    8.
    发明授权
    Apparatus and method for processing data with a plurality of flag groups 失效
    用多个标志组处理数据的装置和方法

    公开(公告)号：US5991868A

    公开(公告)日：1999-11-23

    申请号：US246179

    申请日：1994-05-19

    申请人： Hiroshi Kamiyama ,  Masato Suzuki ,  Shinya Miyaji

    发明人： Hiroshi Kamiyama ,  Masato Suzuki ,  Shinya Miyaji

    IPC分类号： G06F7/00 ,  G06F9/302 ,  G06F9/32 ,  G06F9/30

    CPC分类号： G06F9/30014 ,  G06F9/30058 ,  G06F9/30094

    摘要： In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having different widths, based on the operated results. Selectors select a predetermined flag group in accordance with the direction of a conditional branch instruction. A branch judging unit judges whether a branch is taken or not by referring to the selected flag group.

    摘要翻译： 在数据处理装置中，解码单元解码指令。 计算器根据解码结果来操作N位数据。 标志存储单元基于所操作的结果存储对应于具有不同宽度的数据而改变的多个标志组。 选择器根据条件分支指令的方向选择预定的标志组。 分支判断单元通过参照所选择的标志组判断是否采用分支。

    Processor and control method for performing proper saturation operation
    9.
    发明授权
    Processor and control method for performing proper saturation operation 失效
    用于执行适当饱和运算的处理器和控制方法

    公开(公告)号：US5847978A

    公开(公告)日：1998-12-08

    申请号：US721681

    申请日：1996-09-27

    申请人： Satoshi Ogura ,  Shinya Miyaji ,  Nobuo Higaki ,  Masato Suzuki

    发明人： Satoshi Ogura ,  Shinya Miyaji ,  Nobuo Higaki ,  Masato Suzuki

    IPC分类号： G06F7/38 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305

    CPC分类号： G06F7/57 ,  G06F9/3001 ,  G06F2207/382 ,  G06F7/49921

    摘要： A processor including an arithmetic operation circuit and a saturation operation correction circuit both of which are connected in parallel to a register and a data bus and are activated by respective operation instructions. The saturation operation correction circuit judges whether an output from a register file exceeds either of a predetermined upper-most value and a predetermined lower-most value, and selectively outputs one of an operation result, the upper-most value, and the lower-most value.

    摘要翻译： 一种处理器，包括算术运算电路和饱和运算校正电路，二者并联连接到寄存器和数据总线，并由相应的操作指令激活。 饱和运算校正电路判断来自寄存器堆的输出是否超过预定的最高值和预定的最低值，并且选择性地输出运算结果，最高值和最低者 值。

    Information processing apparatus for realizing data transfer for a plurality of registers using instructions of short word length
    10.
    发明授权
    Information processing apparatus for realizing data transfer for a plurality of registers using instructions of short word length 失效
    用于使用短字长指令实现多个寄存器的数据传送的信息处理设备

    公开(公告)号：US5796970A

    公开(公告)日：1998-08-18

    申请号：US716946

    申请日：1996-09-20

    申请人： Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji ,  Shuichi Takayama

    发明人： Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji ,  Shuichi Takayama

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/34 ,  G06F9/345

    CPC分类号： G06F9/30043 ,  G06F9/30138 ,  G06F9/3016

    摘要： An information processing apparatus for executing a program, the apparatus including: a register set made up of a plurality of registers; a decoding unit for decoding machine language instructions in the program and extracting a selected instruction which indicates data transfer between a plurality of registers designated by a first operand, which is made up of a single field of at least one bit which shows whether an individual register out of the register set is designated and a group field which shows whether a plurality of other registers out of the register set are designated as a group, and consecutive addresses of memory designated by a second operand as an effective address of memory; a determining unit for determining whether each bit in the single field and group field of the first operand of the extracted machine language instruction is valid; a first generating unit for generating a register number for a register corresponding to a bit determined as being valid in the single field, a second generating unit for generating in order a register number of each register to which the group field relates, when a bit in the group field has been determined as being valid; and a transferring unit for executing data transfer between the registers identified by the register numbers generated by the first generating unit and the second generating unit and the consecutive memory areas starting from the effective address.

    摘要翻译： 一种用于执行程序的信息处理装置，所述装置包括：由多个寄存器组成的寄存器组; 解码单元，用于对程序中的机器语言指令进行解码，并提取指示由第一操作数指定的多个寄存器之间的数据传送的选择指令，该第一操作数由至少一位的单个字段组成，其显示单个寄存器 指定寄存器组中的多个其他寄存器被指定为组，并且将由第二操作数指定的存储器的连续地址指定为存储器的有效地址的组字段; 确定单元，用于确定所提取的机器语言指令的第一操作数的单个字段和组字段中的每个位是否有效; 第一生成单元，用于生成对应于在单个字段中被确定为有效的比特的寄存器的寄存器号;第二生成单元，用于按顺序生成与组域相关的每个寄存器的寄存器号， 组合领域已被确定为有效; 以及传送单元，用于执行由由第一生成单元和第二生成单元生成的寄存器号码识别的寄存器和从有效地址开始的连续存储区域之间的数据传送。