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    Semiconductor Devices and Methods of Manufacture
    81.
    发明申请
    Semiconductor Devices and Methods of Manufacture 有权

    公开(公告)号：US20210280415A1

    公开(公告)日：2021-09-09

    申请号：US17321691

    申请日：2021-05-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yen Peng ,  Te-Yang Lai ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

    Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

    Semiconductor Device and Method
    84.
    发明申请
    Semiconductor Device and Method 有权

    公开(公告)号：US20210242327A1

    公开(公告)日：2021-08-05

    申请号：US16940226

    申请日：2020-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

    IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

    Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

    SEMICONDUCTOR DEVICE AND METHOD
    85.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD 有权

    公开(公告)号：US20210202697A1

    公开(公告)日：2021-07-01

    申请号：US16806366

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265

    Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

    SYSTEM-ON-CHIP WITH FERROELECTRIC RANDOM ACCESS MEMORY AND TUNABLE CAPACITOR
    86.
    发明申请
    SYSTEM-ON-CHIP WITH FERROELECTRIC RANDOM ACCESS MEMORY AND TUNABLE CAPACITOR 有权

    公开(公告)号：US20210202511A1

    公开(公告)日：2021-07-01

    申请号：US16904717

    申请日：2020-06-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Chenchen Jacob Wang

    IPC: H01L27/11509 ,  H01L27/11507 ,  H01L49/02

    Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.

    Low-K Gate Spacer and Formation Thereof
    90.
    发明申请
    Low-K Gate Spacer and Formation Thereof 审中-公开

    公开(公告)号：US20200075419A1

    公开(公告)日：2020-03-05

    申请号：US16674443

    申请日：2019-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

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