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    FLIP-CHIP PROCESS AND BONDING EQUIPMENT
    82.
    发明申请
    FLIP-CHIP PROCESS AND BONDING EQUIPMENT 有权

    公开(公告)号：US20220406642A1

    公开(公告)日：2022-12-22

    申请号：US17392462

    申请日：2021-08-03

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Yu-Lung Huang ,  Chih-Ming Huang ,  Kuo-Hua Yu ,  Chang-Fu Lin

    IPC: H01L21/683 ,  H01L23/00

    Abstract: A flip-chip process is to provide a pressing jig with a channel, so that the pressing jig grips a chip module by vacuum suction through the channel, and the chip module can be bonded onto a circuit board via a plurality of solder bumps through the pressing jig, and then a heating device is provided to heat the plurality of solder bumps and reflow the plurality of solder bumps. Therefore, the chip module can be vacuum-gripped by the pressing jig to suppress deformation of the chip module, so that the solder bumps can effectively connect to corresponding contacts of the circuit board.

    Electronic package, manufacturing method thereof and conductive structure
    85.
    发明授权
    Electronic package, manufacturing method thereof and conductive structure 有权

    公开(公告)号：US11410954B2

    公开(公告)日：2022-08-09

    申请号：US16922169

    申请日：2020-07-07

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Yuan-Hung Hsu

    IPC: H01L23/00

    Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate.

    ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
    87.
    发明申请
    ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220068663A1

    公开(公告)日：2022-03-03

    申请号：US17068988

    申请日：2020-10-13

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Yu-Lung Huang ,  Chih-Ming Huang ,  Kuo-Hua Yu ,  Chang-Fu Lin

    IPC: H01L21/48 ,  H01L23/498

    Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.

    METHOD FOR FABRICATING ELECTRONIC PACKAGE
    88.
    发明申请
    METHOD FOR FABRICATING ELECTRONIC PACKAGE 有权

    公开(公告)号：US20210296295A1

    公开(公告)日：2021-09-23

    申请号：US17337752

    申请日：2021-06-03

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Kong-Toon Ng ,  Hung-Ho Lee ,  Chee-Key Chung ,  Chang-Fu Lin ,  Chi-Hsin Chiu

    IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

    Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
    89.
    发明申请
    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20210287962A1

    公开(公告)日：2021-09-16

    申请号：US16872740

    申请日：2020-05-12

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Yuan-Hung Hsu

    IPC: H01L23/433 ,  H01L21/48 ,  H01L23/00

    Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.

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