公开(公告)号：US20190026627A1

公开(公告)日：2019-01-24

申请号：US15891220

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G06N3/063 ,  G06N3/04

Abstract: A neuromorphic architecture for providing variable precision in a neural network, through programming. Logical pre-synaptic neurons are formed as configurable sets of physical pre-synaptic artificial neurons, logical post-synaptic neurons are formed as configurable sets of physical post-synaptic artificial neurons, and the logical pre-synaptic neurons are connected to the logical post-synaptic neurons by logical synapses each including a set of physical artificial synapses. The precision of the weights of the logical synapses may be varied by varying the number of physical pre-synaptic artificial neurons in each of the logical pre-synaptic neurons, and/or by varying the number of physical post-synaptic artificial neurons in each of the logical post-synaptic neurons.

公开(公告)号：US20190012593A1

公开(公告)日：2019-01-10

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/423

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US10026652B2

公开(公告)日：2018-07-17

申请号：US15343157

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.

公开(公告)号：US10008580B2

公开(公告)日：2018-06-26

申请号：US15346535

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66856 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1-xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1-xA, wherein x is not 0.53.

公开(公告)号：US09711414B2

公开(公告)日：2017-07-18

申请号：US14887484

申请日：2015-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823828 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/775 ,  H01L29/7847

Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

公开(公告)号：US09484423B2

公开(公告)日：2016-11-01

申请号：US14270690

申请日：2014-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Jorge A. Kittl ,  Mark. S. Rodder

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/78681 ,  H01L29/78696

Abstract: A field effect transistor includes a body layer comprising a crystalline semiconductor channel region therein, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer, and a crystalline semiconductor gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Abstract translation: 场效应晶体管包括其中包括晶体半导体沟道区的主体层，以及沟道区上的栅叠层。 栅极堆叠包括晶体半导体栅极层和栅极层和沟道区之间的晶体半导体栅极介电层。 还讨论了相关设备和制造方法。

公开(公告)号：US09425275B2

公开(公告)日：2016-08-23

申请号：US14728104

申请日：2015-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Dharmendar Reddy Palle ,  Borna J. Obradovic

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886

Abstract: An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.

Abstract translation: 集成电路芯片包括半导体衬底，第一后端线单元电路，其包括第一组场效应晶体管，第二栅极负载单元电路，其包括第二组场效应晶体管。 第一组场效应晶体管包括第一晶体管，第二组场效应晶体管包括第二晶体管。 与第二晶体管的栅电极的底表面相比，第一晶体管的栅电极的底表面比半导体衬底的底表面更靠近。

公开(公告)号：US20150364556A1

公开(公告)日：2015-12-17

申请号：US14728104

申请日：2015-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. RODDER ,  Dharmendar Reddy PALLE ,  Borna J. Obradovic

IPC: H01L29/423 ,  H01L27/088

CPC classification number: H01L29/4238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886

Abstract: An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.

Abstract translation: 集成电路芯片包括半导体衬底，第一后端线单元电路，其包括第一组场效应晶体管，第二栅极负载单元电路，其包括第二组场效应晶体管。 第一组场效应晶体管包括第一晶体管，第二组场效应晶体管包括第二晶体管。 与第二晶体管的栅电极的底表面相比，第一晶体管的栅电极的底表面比半导体衬底的底表面更靠近。