公开(公告)号：US20160078794A1

公开(公告)日：2016-03-17

申请号：US14534167

申请日：2014-11-06

Applicant: Novatek Microelectronics Corp.

Inventor： Po-Yu Tseng ,  Jhih-Siou Cheng ,  Pang-Chen Hung

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0264 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2330/025 ,  G09G2330/045

Abstract: A driving device and a source driving method are provided. The driving device includes a first code mapping unit, a first source driving channel, a second code mapping unit and a second source driving channel. The first code mapping unit converts a first input code in input data into a first intermediate code according to a first code-to-code mapping relation. The first source driving channel converts the first intermediate code into a first analog voltage according to a first code-to-voltage mapping relation. The second code mapping unit converts a second input code in the input data into a second intermediate code according to a second code-to-code mapping relation which is different from the first code-to-code mapping relation. The second source driving channel converts the second intermediate code into a second analog voltage according to a second code-to-voltage mapping relation which is different from the first code-to-voltage mapping relation.

Abstract translation: 提供驱动装置和源驱动方法。 驱动装置包括第一码映射单元，第一源驱动信道，第二码映射单元和第二源驱动信道。 第一代码映射单元根据第一代码映射关系将输入数据中的第一输入代码转换为第一中间代码。 第一源驱动通道根据第一代码电压映射关系将第一中间代码转换成第一模拟电压。 第二代码映射单元根据与第一代码到代码映射关系不同的第二代码到代码映射关系将输入数据中的第二输入代码转换为第二中间代码。 第二源极驱动通道根据与第一代码电压映射关系不同的第二代码到电压映射关系将第二中间代码转换成第二模拟电压。

公开(公告)号：US09245857B2

公开(公告)日：2016-01-26

申请号：US14726613

申请日：2015-06-01

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/60 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H02H9/02

CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

公开(公告)号：US20150381197A1

公开(公告)日：2015-12-31

申请号：US14845289

申请日：2015-09-04

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Ju-Lin Huang ,  Pang-Chan Hung

IPC: H03M1/76 ,  G09G3/20

CPC classification number: H03M1/76 ,  G09G3/2007 ,  G09G3/3291 ,  G09G3/3696 ,  G09G5/02 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/028 ,  H03K3/01 ,  H03M1/66 ,  H03M1/765

Abstract: A digital to analog converter is disclosed. The invention provides a digital to analog converter (DAC) including a plurality of voltage transmitting switches and a selecting signal decoder. The voltage transmitting switches respectively receive a plurality of input voltages, and output terminals of the voltage transmitting switches are commonly coupled to an output terminal of the digital to analog converter. The selecting signal decoder receives a plurality of selecting signals, and generates a plurality of transmitting enable signals to control the voltage transmitting switches. Wherein only one of the voltage transmitting switches is connected between each of the input voltages and the output terminal of the digital to analog converter.

Abstract translation: 公开了一种数模转换器。 本发明提供一种包括多个电压发射开关和选择信号解码器的数模转换器（DAC）。 电压发送开关分别接收多个输入电压，电压发送开关的输出端子共同耦合到数模转换器的输出端子。 选择信号解码器接收多个选择信号，并且产生多个发送使能信号以控制电压发送开关。 其中只有一个电压发射开关连接在每个输入电压和数模转换器的输出端之间。

公开(公告)号：US08797201B2

公开(公告)日：2014-08-05

申请号：US13925849

申请日：2013-06-25

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

IPC: H03M1/66

CPC classification number: H03M1/06 ,  G09G3/20 ,  G09G2300/0421 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2320/0276 ,  H03M1/66 ,  H03M1/765

Abstract: A driving circuit includes a plurality of reference voltage lines and a digital to analog converter. The reference voltage lines are configured for respectively transmitting different grayscale reference voltages, in which the grayscale reference voltages are divided into at least two groups, and the wire diameter/wire width of at least one reference voltage line among the reference voltage lines of a first voltage group among the at least two groups is different from the wire diameters/wire widths of the reference voltage lines of a second voltage group among the at least two groups. The digital to analog converter is coupled to the reference voltage lines to receive the grayscale reference voltages and is for converting a digital signal into a grayscale voltage according to the grayscale reference voltages.

Abstract translation: 驱动电路包括多个参考电压线和数模转换器。 参考电压线被配置为分别传输不同的灰度参考电压，其中灰度参考电压被划分为至少两组，并且第一个参考电压的参考电压线中的至少一个参考电压线的线径/线宽 所述至少两组中的电压组与所述至少两组中的第二电压组的参考电压线的线径/线宽不同。 数模转换器耦合到参考电压线以接收灰度参考电压，并且用于根据灰度参考电压将数字信号转换成灰度级电压。

公开(公告)号：US20250007475A1

公开(公告)日：2025-01-02

申请号：US18624110

申请日：2024-04-01

Applicant: NOVATEK Microelectronics Corp.

Inventor： Jui-Chan Chang ,  Jhih-Siou Cheng ,  Ren-Chieh Yang ,  Jin-Yi Lin

IPC: H03F3/45

Abstract: A calibration circuit of a differential difference amplifier (DDA) includes a trimming circuit, a bias generator and a compensation output circuit. The trimming circuit is used to output a trimming code. The bias generator, coupled to the trimming circuit, is used to generate a bias current or voltage according to the trimming code. The compensation output circuit, coupled to the bias generator, is used to receive a data code of the DDA and output the bias current or voltage corresponding to the data code to the DDA.

公开(公告)号：US12100339B1

公开(公告)日：2024-09-24

申请号：US18196415

申请日：2023-05-11

Applicant: NOVATEK Microelectronics Corp.

Inventor： Yi-Yang Tsai ,  Po-Hsiang Fang ,  Jhih-Siou Cheng

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0202 ,  G09G2310/0208 ,  G09G2310/0267 ,  G09G2310/08

Abstract: A method of scanning a display panel having a plurality of rows of pixels includes steps of: generating a first accumulated number; calculating a first scan number according to the first accumulated number; scanning a present row of pixels having the first scan number among the plurality of rows of pixels; accumulating the first accumulated number to generate a second accumulated number; calculating a second scan number according to the second accumulated number; and scanning a next row of pixels having the second scan number among the plurality of rows of pixels after scanning the present row of pixels. Wherein, the plurality of rows of pixels are scanned in a scan order different from a numbering order of the plurality of rows of pixels.

公开(公告)号：US12081232B2

公开(公告)日：2024-09-03

申请号：US17827822

申请日：2022-05-30

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Chih-Hsien Chou ,  Chieh-An Lin

IPC: H03M1/66 ,  G09G3/20

CPC classification number: H03M1/661 ,  G09G3/2007 ,  G09G2310/027 ,  G09G2310/0289

Abstract: The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.

公开(公告)号：US11978392B1

公开(公告)日：2024-05-07

申请号：US18203652

申请日：2023-05-31

Applicant: NOVATEK Microelectronics Corp.

Inventor： Min-Yang Chiu ,  Yu-Sheng Ma ,  Jin-Yi Lin ,  Hsuan-Yu Chen ,  Jhih-Siou Cheng ,  Chun-Fu Lin

IPC: G09G3/00 ,  G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0248 ,  G09G2310/0272 ,  G09G2310/0291 ,  G09G2310/08

Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.

公开(公告)号：US11948518B2

公开(公告)日：2024-04-02

申请号：US18203651

申请日：2023-05-31

Applicant: NOVATEK Microelectronics Corp.

Inventor： Jhih-Siou Cheng

IPC: G09G3/3291 ,  G09G3/20

CPC classification number: G09G3/3291 ,  G09G3/2074 ,  G09G2300/0452 ,  G09G2310/027 ,  G09G2320/0626 ,  G09G2320/0673 ,  G09G2330/028

Abstract: A source driver includes a first DAC for driving a first-color subpixel and a second DAC for driving a second-color subpixel. Each DAC is configured to output at least one output voltage according to an N-bit data code, and includes a plurality of sub-DACs, an interpolation circuit and a switch circuit. Each sub-DAC receives m bits of the N-bit data code and generates a set of intermediate voltages accordingly. The interpolation circuit performs an interpolation on a selected set of intermediate voltages according to k bits of the N-bit data code and at least one interpolation control signal, to generate the output voltage. The switch circuit electrically connects the interpolation circuit and a selected sub-DAC which outputs the selected set of intermediate voltages. The interpolation circuit of the first DAC and the interpolation circuit of the second DAC respectively perform the interpolation according to different numbers of interpolation bits.

公开(公告)号：US11881136B2

公开(公告)日：2024-01-23

申请号：US17646198

申请日：2021-12-28

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jhih-Siou Cheng ,  Yen-Ru Kuo ,  Chih-Hsien Chou

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/021

Abstract: A display driver and a driving method thereof is disclosed. The display driver includes at least one first latch, at least one second latch, an output buffer, and a comparator. The first latch receives input data. The input terminal of the second latch is coupled to the output terminal of the first latch. The output buffer, including at least one variable current source, is coupled to the second latch. The comparator is coupled to the first latch, the second latch, and the variable current source. The comparator generates at least one control signal of the variable current source.