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公开(公告)号:US12094383B2
公开(公告)日:2024-09-17
申请号:US18172291
申请日:2023-02-21
Applicant: Novatek Microelectronics Corp.
Inventor: Chieh-An Lin , Keko-Chun Liang , Jhih-Siou Cheng
CPC classification number: G09G3/20 , H02J7/345 , G09G2310/0202 , G09G2310/0248 , G09G2310/027 , G09G2310/0289 , G09G2310/0291 , G09G2330/021
Abstract: A display driver and a charge recycling method are provided. The display driver includes a charging and discharging circuit and a control circuit. A first terminal of the charging and discharging circuit is coupled to at least one of the scan lines, and a second terminal of the charging and discharging circuit is coupled to at least one of the data lines. The control circuit is coupled to a first control terminal and a second control terminal of the charging and discharging circuit. The charging and discharging circuit receives a first current generated by discharging the at least one of the scan lines to charge the capacitor based on a first control signal. The charging and discharging circuit discharges the capacitor to generate a second current for charging the at least one of the data lines based on a second control signal.
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公开(公告)号:US20240282231A1
公开(公告)日:2024-08-22
申请号:US18172291
申请日:2023-02-21
Applicant: Novatek Microelectronics Corp.
Inventor: Chieh-An Lin , Keko-Chun Liang , Jhih-Siou Cheng
CPC classification number: G09G3/20 , H02J7/345 , G09G2310/0202 , G09G2310/0248 , G09G2310/027 , G09G2310/0289 , G09G2310/0291 , G09G2330/021
Abstract: A display driver and a charge recycling method are provided. The display driver includes a charging and discharging circuit and a control circuit. A first terminal of the charging and discharging circuit is coupled to at least one of the scan lines, and a second terminal of the charging and discharging circuit is coupled to at least one of the data lines. The control circuit is coupled to a first control terminal and a second control terminal of the charging and discharging circuit. The charging and discharging circuit receives a first current generated by discharging the at least one of the scan lines to charge the capacitor based on a first control signal. The charging and discharging circuit discharges the capacitor to generate a second current for charging the at least one of the data lines based on a second control signal.
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公开(公告)号:US12051381B2
公开(公告)日:2024-07-30
申请号:US18167896
申请日:2023-02-13
Applicant: Novatek Microelectronics Corp.
Inventor: Yi-Yang Tsai , Hung-Ho Huang , Tzong-Honge Shieh , Chieh-An Lin , Po-Hsiang Fang , Jhih-Siou Cheng
IPC: G09G3/34
CPC classification number: G09G3/3406 , G09G2310/0237 , G09G2320/0261 , G09G2320/064 , G09G2330/021 , G09G2370/00
Abstract: The disclosure provides a control method of a display driver. The control method includes receiving address information and defining an IC address according to the address information. The IC address includes n bits representing k zones, and n and k are positive integers. The control method further includes receiving the IC address, a black frame data signal and a pulse-width modulation (PWM) signal, and turning on or off the plurality of LEDs in the corresponding zone according to toggle of bit in the black frame data signal. Each bit in the black frame data signal indicates that a plurality of LEDs in a zone among the k zones are turned on or off.
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公开(公告)号:US20240096289A1
公开(公告)日:2024-03-21
申请号:US18167896
申请日:2023-02-13
Applicant: Novatek Microelectronics Corp.
Inventor: Yi-Yang Tsai , Hung-Ho Huang , Tzong-Honge Shieh , Chieh-An Lin , Po-Hsiang Fang , Jhih-Siou Cheng
IPC: G09G3/34
CPC classification number: G09G3/3406 , G09G2310/0237 , G09G2320/0261 , G09G2320/064 , G09G2330/021 , G09G2370/00
Abstract: The disclosure provides a control method of a display driver. The control method includes receiving address information and defining an IC address according to the address information. The IC address includes n bits representing k zones, and n and k are positive integers. The control method further includes receiving the IC address, a black frame data signal and a pulse-width modulation (PWM) signal, and turning on or off the plurality of LEDs in the corresponding zone according to toggle of bit in the black frame data signal. Each bit in the black frame data signal indicates that a plurality of LEDs in a zone among the k zones are turned on or off.
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公开(公告)号:US20240046856A1
公开(公告)日:2024-02-08
申请号:US18365247
申请日:2023-08-04
Applicant: Novatek Microelectronics Corp.
Inventor: Yu-Sheng Ma , Jhih-Siou Cheng , Chun-Fu Lin , Jin-Yi Lin
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0275 , G09G2310/0267 , G09G2310/0251 , G09G2330/04
Abstract: A light-emitting diode (LED) panel and a driving device therefore is provided. The driving device includes a source driver and a scan driver. The source driver is coupled to a plurality of data lines disposed in the LED panel. The source driver outputs driving currents to the data lines in any one of a plurality of scan line periods, to drive an LED array of the LED panel. The scan driver is coupled to a plurality of scan lines disposed in the LED panel, wherein the scan driver scans the scan lines during the plurality of scan line periods. In an active period of any one of the scan line periods, the scan driver applies an enable voltage to a current scan line among the scan lines, and the scan driver applies a pre-charge voltage to other scan line among the scan lines.
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公开(公告)号:US20230387937A1
公开(公告)日:2023-11-30
申请号:US17827822
申请日:2022-05-30
Applicant: Novatek Microelectronics Corp.
Inventor: Jhih-Siou Cheng , Chih-Hsien Chou , Chieh-An Lin
CPC classification number: H03M1/661 , G09G3/2007 , G09G2310/027 , G09G2310/0289
Abstract: The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.
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公开(公告)号:US20230386415A1
公开(公告)日:2023-11-30
申请号:US18203651
申请日:2023-05-31
Applicant: NOVATEK Microelectronics Corp.
Inventor: Jhih-Siou Cheng
IPC: G09G3/3291
CPC classification number: G09G3/3291 , G09G2310/027 , G09G2320/0673 , G09G2300/0452 , G09G2320/0626 , G09G2330/028 , G09G3/2074
Abstract: A source driver includes a first DAC for driving a first-color subpixel and a second DAC for driving a second-color subpixel. Each DAC is configured to output at least one output voltage according to an N-bit data code, and includes a plurality of sub-DACs, an interpolation circuit and a switch circuit. Each sub-DAC receives m bits of the N-bit data code and generates a set of intermediate voltages accordingly. The interpolation circuit performs an interpolation on a selected set of intermediate voltages according to k bits of the N-bit data code and at least one interpolation control signal, to generate the output voltage. The switch circuit electrically connects the interpolation circuit and a selected sub-DAC which outputs the selected set of intermediate voltages. The interpolation circuit of the first DAC and the interpolation circuit of the second DAC respectively perform the interpolation according to different numbers of interpolation bits.
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公开(公告)号:US20230378972A1
公开(公告)日:2023-11-23
申请号:US18106470
申请日:2023-02-06
Applicant: NOVATEK Microelectronics Corp.
Inventor: Jin-Yi Lin , Jhih-Siou Cheng , Yung-Te Chang , Chih-Cheng Chen
CPC classification number: H03M1/468 , H03M1/1245 , H03M1/462 , H03M1/145
Abstract: A sample and hold (S/H) circuit includes an analog-to-digital converter (ADC), a register and a digital-to-analog converter (DAC). The ADC receives an input signal and converts the input signal into a digital code. The register, coupled to the ADC, stores the digital code. The DAC, coupled to the register, converts the digital code into an output signal.
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公开(公告)号:US20230306900A1
公开(公告)日:2023-09-28
申请号:US18205199
申请日:2023-06-02
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor: Yu-Sheng Ma , Jhih-Siou Cheng , Chun-Fu Lin , Jin-Yi Lin , Ju-Lin Huang
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2320/064 , G09G2330/021
Abstract: The present disclosure relates to a driver for driving a light emitting unit array of a display device, the driver including: a plurality of driving units, each of the plurality of driving units includes: a driving circuit configured to provide a driving current to a corresponding column of light emitting units in the light emitting unit array according to a pulse width modulation signal, during a turn-on period of a channel switch; a charge path circuit configured to be connected in parallel with the driving circuit, and to be turned on during the turn-on period of the channel switch to form a charge path; and a discharge path circuit configured to be connected in parallel with the driving circuit, and to be turned-on after the channel switch is turned off, to form a discharge path.
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公开(公告)号:US20230269845A1
公开(公告)日:2023-08-24
申请号:US17964059
申请日:2022-10-12
Applicant: NOVATEK Microelectronics Corp.
Inventor: Chih-Hsien Chou , Jhih-Siou Cheng , Jin-Yi Lin , Ren-Chieh Yang
IPC: H05B45/325 , H05B45/46 , H05B45/345 , H05B45/54 , G09G3/32
CPC classification number: H05B45/325 , H05B45/46 , H05B45/345 , H05B45/54 , G09G3/32
Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.
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