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    CAPACITOR STRUCTURE
    82.
    发明申请
    CAPACITOR STRUCTURE 审中-公开
    电容结构

    公开(公告)号：US20060258113A1

    公开(公告)日：2006-11-16

    申请号：US11460021

    申请日：2006-07-26

    Applicant: Gurtej Sandhu ,  Guy Blalock

    Inventor： Gurtej Sandhu ,  Guy Blalock

    IPC: H01L29/94 ,  H01L21/20

    CPC classification number: H01L27/10852 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31637 ,  H01L21/31654 ,  H01L27/10811 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/56 ,  H01L28/65 ,  H01L28/91

    Abstract: A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as opposed to a depositing a single thick layer. Further, at least one of the oxidation steps is less aggressive than the oxidation environment or environments that would be used to deposit the single thick layer. This allows greater control over oxidizing the dielectric and other components beyond the dielectric.

    Abstract translation: 描述电容器结构及其形成方法。 特别地，提供高K电介质氧化物作为电容器电介质。 与沉积单个厚层相反，高K电介质沉积在一系列薄层中并在一系列氧化步骤中被氧化。 此外，至少一个氧化步骤比用于沉积单个厚层的氧化环境或环境更不具有侵蚀性。 这允许更好地控制电介质和超过电介质的其它组件的氧化。

    Deposition methods
    84.
    发明申请
    Deposition methods 审中-公开
    沉积方法

    公开(公告)号：US20060257570A1

    公开(公告)日：2006-11-16

    申请号：US11490622

    申请日：2006-07-21

    Applicant: Garo Derderian ,  Gurtej Sandhu

    Inventor： Garo Derderian ,  Gurtej Sandhu

    IPC: C23C16/00

    CPC classification number: C23C16/45525 ,  B05D1/185 ,  C23C16/04 ,  C23C16/045 ,  C23C16/403 ,  C23C16/45531 ,  C30B25/18 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162

    Abstract: A deposition method includes contacting a substrate with a first initiation precursor and forming a first portion of an initiation layer on the substrate. At least a part of the substrate is contacted with a second initiation precursor different from the first initiation precursor and a second portion of the initiation layer is formed on the substrate. The substrate may be simultaneously contacted with a plurality of initiation precursors, forming on the substrate and initiation layer comprising components, derived from each of the plurality of initiation precursors. An initiation layer may be contacted with a deposition precursor, forming a deposition layer on the initiation layer. The deposition layer may be contacted with a second initiation precursor different from the first initiation precursor forming a second initiation layer over the substrate. Also, a first initiation layer may be formed substantially selectively on a first-type substrate surface relative to a second-type substrate surface and contacted with a deposition precursor, forming a deposition layer substantially selectively over the first-type substrate surface.

    Abstract translation: 沉积方法包括使基底与第一起始前体接触，并在基底上形成起始层的第一部分。 基板的至少一部分与不同于第一起始前体的第二起始前体接触，并且在基板上形成起始层的第二部分。 衬底可以与多个起始前体同时接触，在衬底上形成并且起始层包含衍生自多个引发前体中的每一个的组分。 引发层可以与沉积前体接触，在引发层上形成沉积层。 沉积层可以与不同于第一起始前体的第二引发前体接触，从而在衬底上形成第二起始层。 此外，第一起始层可以基本上选择性地形成在相对于第二类型衬底表面的第一类型衬底表面上，并与沉积前体接触，在第一类型衬底表面上基本上选择性地形成沉积层。

    One-transistor composite-gate memory
    85.
    发明申请
    One-transistor composite-gate memory 有权

    公开(公告)号：US20060255400A1

    公开(公告)日：2006-11-16

    申请号：US11489880

    申请日：2006-07-20

    Applicant: Cem Basceri ,  Gurtej Sandhu

    Inventor： Cem Basceri ,  Gurtej Sandhu

    IPC: H01L29/792

    CPC classification number: G11C11/5671 ,  G11C8/12 ,  G11C16/0416 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

    Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

    RESISTIVE HEATER FOR THERMO OPTIC DEVICE
    86.
    发明申请
    RESISTIVE HEATER FOR THERMO OPTIC DEVICE 有权
    热电器件电阻式加热器

    公开(公告)号：US20060228084A1

    公开(公告)日：2006-10-12

    申请号：US11424401

    申请日：2006-06-15

    Applicant: Gurtej Sandhu ,  Guy Blalock

    Inventor： Gurtej Sandhu ,  Guy Blalock

    IPC: G02B6/10

    CPC classification number: G02B6/125 ,  G02F1/0102 ,  G02F1/0147 ,  G02F1/2257 ,  G02F2201/30 ,  G02F2201/307 ,  G02F2202/104

    Abstract: Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing methods. The resistive heater is comprised of a heater region and a conductive path region formed together in a first mask count from a relatively high resistance material. A conductor formed from a relatively low resistance material is formed directly on the conductive path region in a second mask count. Thermo optic devices formed by these two mask count methods are also described.

    Abstract translation: 在热光器件的光栅的表面上形成两个掩模计数的电阻加热器，从而从现有技术的制造方法中消除一个掩模计数。 电阻加热器包括加热器区域和形成在来自相对高电阻材料的第一掩模计数中的导电路径区域。 由相对低电阻材料形成的导体以第二掩模计数直接形成在导电路径区域上。 还描述了通过这两种掩模计数方法形成的热光学器件。

    Antireflective coating for use during the manufacture of a semiconductor device
    87.
    发明申请
    Antireflective coating for use during the manufacture of a semiconductor device 审中-公开
    在制造半导体器件期间使用的抗反射涂层

    公开(公告)号：US20060220184A1

    公开(公告)日：2006-10-05

    申请号：US11214376

    申请日：2005-08-29

    Applicant: Zhiping Yin ,  Gurtej Sandhu

    Inventor： Zhiping Yin ,  Gurtej Sandhu

    IPC: H01L23/58

    CPC classification number: H01L27/10888 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/90

    Abstract: An antireflective layer formed from boron-doped amorphous carbon may be removed using a process which is less likely to over etch a dielectric layer than conventional technology. This layer may be removed by exposing the layer to an oxygen plasma (i.e. an “ashing” process), preferably concurrently with the ashing and removal of an overlying photoresist layer. An inventive process which uses the inventive antireflective layer is also described.

    Abstract translation: 可以使用与常规技术相比不太可能过蚀刻电介质层的方法来去除由硼掺杂的非晶碳形成的抗反射层。 可以通过将层暴露于氧等离子体（即，“灰化”工艺），优选地与上覆的光致抗蚀剂层的灰化和去除同时地去除该层。 还描述了使用本发明的抗反射层的本发明的方法。

    Pitch reduced patterns relative to photolithography features
    88.
    发明申请
    Pitch reduced patterns relative to photolithography features 有权
    相对于光刻特征的间距减小

    公开(公告)号：US20060211260A1

    公开(公告)日：2006-09-21

    申请号：US11214544

    申请日：2005-08-29

    Applicant: Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    Inventor： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    IPC: H01L21/31

    CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

    Abstract translation: 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

    High coupling memory cell
    89.
    发明申请
    High coupling memory cell 审中-公开

    公开(公告)号：US20060211201A1

    公开(公告)日：2006-09-21

    申请号：US11440351

    申请日：2006-05-24

    Applicant: Sukesh Sandhu ,  Gurtej Sandhu

    Inventor： Sukesh Sandhu ,  Gurtej Sandhu

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

    Abstract: A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

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