公开(公告)号：US20250157980A1

公开(公告)日：2025-05-15

申请号：US18741540

申请日：2024-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong SEOL

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes semiconductor chips each including at least one of a front insulating layer or a rear insulating layer, the semiconductor chips bonded to each other through direct bonding between the front insulating layer and the rear insulating layer. At least one of the semiconductor chips includes a device layer including an interconnection structure, and a conductive pattern on a front surface of the device layer. The conductive pattern includes pad patterns electrically connected to the interconnection structure, and a dummy pattern spaced apart from the pad patterns. The dummy pattern includes first dummy patterns between the pad patterns to overlap the pad patterns in a first direction, and a second dummy patterns between the first dummy patterns to overlap the pad patterns in the second direction. The second dummy patterns are spaced apart from the first dummy patterns.

公开(公告)号：US20250157948A1

公开(公告)日：2025-05-15

申请号：US19023084

申请日：2025-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Yeonjin Lee ,  Jeonil Lee ,  Jongmin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

公开(公告)号：US20250157921A1

公开(公告)日：2025-05-15

申请号：US18740739

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeewoong Kim ,  Seunghun Lee ,  Kyowook Lee ,  Keunhwi Cho

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

Abstract: Provided is an integrated circuit device with reduced line margins. The integrated circuit device includes an active area on a substrate, a channel area in the active area, a gate line that extends around the channel area, a plurality of first upper lines that electrically connect the channel area and the gate line to each other, a plurality of first lower lines of a side of the substrate, and a second lower wiring line on a side of the plurality of first lower lines that is opposite the substrate. The plurality of first lower lines includes a jog pattern line and an island pattern line that is spaced apart from the jog pattern line, and the island pattern line is electrically connected to the second lower wiring line by a lower contact.

公开(公告)号：US20250157916A1

公开(公告)日：2025-05-15

申请号：US18651944

申请日：2024-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEMYUNG CHOI ,  KANG-ILL SEO

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Integrated circuit (IC) devices are provided. An IC device includes a back-end-of-line (BEOL) region that includes a first via and a second via on a first lower metal line and a second lower metal line, respectively. The BEOL region includes a first upper metal line coupled to the first lower metal line by the first via, and a second upper metal line coupled to the second lower metal line by the second via. The first upper metal line and the first via each include a first metal. The second upper metal line and the second via each include a second metal that is different from the first metal. Moreover, the second upper metal line is wider than the first upper metal line. Related methods of forming BEOL regions of IC devices are also provided.

公开(公告)号：US20250157902A1

公开(公告)日：2025-05-15

申请号：US18938811

申请日：2024-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG ,  Kiju LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes: a first redistribution structure; a second redistribution structure arranged on the first redistribution structure; a first conductive pillar arranged spaced apart from the second redistribution structure and arranged on the first redistribution structure; a first chip arranged on the second redistribution structure; a first molding member covering the first chip and disposed on the second redistribution structure; a third redistribution structure arranged on the first molding member; a second chip arranged on the third redistribution structure; a second molding member covering the first conductive pillar and the first molding member; and a fourth redistribution structure arranged on the second molding member, wherein a first film is arranged on a first surface of the first conductive pillar, and the first film includes tin (Sn).

公开(公告)号：US20250157875A1

公开(公告)日：2025-05-15

申请号：US18939702

申请日：2024-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/16 ,  H10B80/00

Abstract: A semiconductor package includes: a first redistribution substrate; a first semiconductor chip on the first redistribution substrate, the first semiconductor chip comprising a semiconductor substrate and a plurality of first thermal vias penetrating through the semiconductor substrate in a first direction; a second semiconductor chip disposed on a center portion of the first semiconductor chip; and a plurality of second thermal vias arranged on a peripheral portion of the first semiconductor chip and arranged on an outer portion of the second semiconductor chip, wherein the plurality of second thermal vias are connected to the plurality of first thermal vias, respectively.

公开(公告)号：US20250157852A1

公开(公告)日：2025-05-15

申请号：US19024215

申请日：2025-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul LEE ,  Ki-Jeong KIM ,  Hwan LIM ,  Hyun-Sil HONG

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H10B12/00 ,  H10D64/27

Abstract: A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.

公开(公告)号：US20250157566A1

公开(公告)日：2025-05-15

申请号：US18670883

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Hui Park ,  Ki-Ho Hyun

IPC: G11C29/00

Abstract: A memory device includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells therein, a fuse array configured to store an address and a master bit of a defective first memory cell therein, and a column decoder configured to select among a plurality of column select lines associated with the normal memory cells and a plurality of spare column select lines associated with the redundant memory cells. The column decoder has a first column repair circuit therein, which includes: (i) a first latch array having a plurality of latch elements therein, which are configured to store a column address of the defective first memory cell, and (ii) first compare logic configured to compare outputs of the plurality of latch elements with an external column address, and generate a first enable signal that indicates whether or not to repair the defective first memory cell, in response to said compare.

公开(公告)号：US20250157518A1

公开(公告)日：2025-05-15

申请号：US18891518

申请日：2024-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwayeong Lee ,  Seulji Song

IPC: G11C11/22 ,  H10B53/30

Abstract: An operating method of a memory device includes, during a write operation, in a first time period, pre-charging a bit line connected to a memory cell with a ground voltage, during the write operation, in a second time period, applying a word line driving voltage to a word line corresponding to the bit line, in the second time period, applying a plate line driving voltage to a plate line connected to the memory cell, and in the second time period, maintaining a voltage applied to the bit line at the ground voltage.

公开(公告)号：US20250157423A1

公开(公告)日：2025-05-15

申请号：US18920570

申请日：2024-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyeok CHOI ,  Daehyun Park ,  Jaein Yoo ,  Kyuheon Lee

IPC: G09G3/34

Abstract: Provided are a display apparatus and an operating method thereof, the display apparatus including: a display; memory storing one or more instructions; and one or more processors configured to execute the one or more instructions stored in the memory, wherein the one or more instructions, when executed by the one or more processors, cause the display apparatus to: obtain, for an image including at least one analysis area, image complexity information of the at least one analysis area, classify the at least one analysis area into a class based on the image complexity information, and generate a dimming control signal configured to control a brightness of the at least one analysis area based on the class.