公开(公告)号：US20090230520A1

公开(公告)日：2009-09-17

申请号：US12453863

申请日：2009-05-26

Applicant: Jong-Joo Lee ,  Mee-Hyun Ahn

Inventor： Jong-Joo Lee ,  Mee-Hyun Ahn

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/49513 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads.

Abstract translation: 本发明提供了各种引线框封装，其中信号连接和固定电压连接被配置为不同以改善连接相对于其分配的功能的相对性能。 信号连接包括一个或多个信号引线和对应的信号接合线的配置，其倾向于减小信号连接器的相对电容，从而提高高速性能。 固定电压连接包括固定电压引线和固定电压接合线的配置，这将降低固定电压连接器的电感，并降低固定电压连接上的噪声，并提高功率输送特性。 相关联的信号和固定电压连接的配置将趋于导致信号连接，其包括与相应的固定电压引线相比更短，更窄和/或更广泛地与半导体芯片的有源表面分离的信号引线。

公开(公告)号：US07462930B2

公开(公告)日：2008-12-09

申请号：US11627791

申请日：2007-01-26

Applicant: Jong-Joo Lee ,  Dong-Ho Lee

Inventor： Jong-Joo Lee ,  Dong-Ho Lee

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

公开(公告)号：US07394160B2

公开(公告)日：2008-07-01

申请号：US11227161

申请日：2005-09-16

Applicant: Moon-Jung Kim ,  Jong-Joo Lee

Inventor： Moon-Jung Kim ,  Jong-Joo Lee

IPC: H01L23/48

CPC classification number: H05K1/181 ,  G11C5/00 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2224/0401

Abstract: An inline memory module (IMM) architecture may include: a printed circuit board (PCB); a first array of memory devices on a first side of the PCB; a second array of memory devices on a second side of the PCB; at least some of the memory devices of the first array being arranged so as to substantially overlap, relative to a reference axis of the PCB, positional-twin memory devices of the second array, respectively; and multiple vias at least some of which are parts of respective signal paths that connect signal leads of a first memory device in the first array to corresponding signal leads of a second memory device in the second array that is adjacent to a positional-twin third memory device in the second array corresponding to the first memory device.

Abstract translation: 在线存储器模块（IMM）架构可以包括：印刷电路板（PCB）; 在PCB的第一侧上的第一阵列存储器件; 在所述PCB的第二侧上的第二阵列存储器件; 第一阵列的至少一些存储器件被布置成相对于PCB的参考轴线基本上重叠，分别位于第二阵列的位置双存储器件; 以及多个通孔，其中至少一些是将第一阵列中的第一存储器件的信号引线连接到第二阵列中的与位置双重第三存储器相邻的第二存储器件的相应信号引线的相应信号路径的部分 第二阵列中的设备对应于第一存储设备。

公开(公告)号：US20080048322A1

公开(公告)日：2008-02-28

申请号：US11837577

申请日：2007-08-13

Applicant: Seung-Duk BAEK ,  Dong-Hyeon JANG ,  Jong-Joo LEE

Inventor： Seung-Duk BAEK ,  Dong-Hyeon JANG ,  Jong-Joo LEE

IPC: H01L23/52

CPC classification number: H01L24/12 ,  H01L21/76807 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014

Abstract: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

Abstract translation: 半导体器件封装包括衬底，在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分，其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线，电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。

公开(公告)号：US20070176268A1

公开(公告)日：2007-08-02

申请号：US11646541

申请日：2006-12-28

Applicant: Jong-Joo Lee ,  Moon-Jung Kim

Inventor： Jong-Joo Lee ,  Moon-Jung Kim

IPC: H01L23/495

CPC classification number: H05K3/368 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/144 ,  H05K3/325 ,  H05K3/326 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/09063 ,  H05K2201/10598 ,  H05K2203/167

Abstract: A semiconductor module may include a printed circuit board that may have a first surface, a second surface, and at least one fixture hole. A semiconductor device may be mounted on the first surface of the printed circuit board. At least one connection terminal may be provided on one of the first surface or the second surface of the printed circuit board that may connect with connection pads of a motherboard. The printed circuit board may be connected to the motherboard through the at least one fixture hole such the connection terminals may be aligned with the connection pad and one of the first surface and second surface of the printed circuit board may face a major surface of the motherboard.

Abstract translation: 半导体模块可以包括可以具有第一表面，第二表面和至少一个固定孔的印刷电路板。 半导体器件可以安装在印刷电路板的第一表面上。 至少一个连接端子可以设置在可与主板的连接焊盘连接的印刷电路板的第一表面或第二表面之一上。 印刷电路板可以通过至少一个固定孔连接到母板，使得连接端子可以与连接垫对准，并且印刷电路板的第一表面和第二表面中的一个可面向主板的主表面 。

公开(公告)号：US20070029663A1

公开(公告)日：2007-02-08

申请号：US11371155

申请日：2006-03-07

Applicant: Moon-Jung Kim ,  Jong-Joo Lee

Inventor： Moon-Jung Kim ,  Jong-Joo Lee

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/49833 ,  H01L23/3114 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A multilayered circuit substrate and a semiconductor package using the multilayered circuit substrate are provided to increase the number of bonding pads arranged on the circuit substrate without reducing the pitch of the bonding pads, and to further increase the routing feasibility of high speed signals by the use of signal wirings instead of vias. An embodiment may include bonding pads provided on different layers, in which the bonding pads arranged on one layer are staggered with the bonding pad arranged on another layer. Ball lands may be connected to the bonding pads using wirings wherein the bonding pads connected to the signal wirings may be provided on the same layer as the corresponding ball lands.

Abstract translation: 提供多层电路基板和使用多层电路基板的半导体封装，以增加布置在电路基板上的接合焊盘的数量，而不会降低焊盘的间距，并且通过使用进一步提高高速信号的布线可行性 的信号线，而不是通孔。 实施例可以包括设置在不同层上的接合焊盘，其中布置在一个层上的接合焊盘与布置在另一层上的焊盘交错布置。 焊盘可以使用布线连接到接合焊盘，其中连接到信号布线的焊盘可以设置在与相应的焊盘相同的层上。

公开(公告)号：US20060194366A1

公开(公告)日：2006-08-31

申请号：US11382245

申请日：2006-05-08

Applicant: Jong-Joo Lee ,  Dong-Ho Lee

Inventor： Jong-Joo Lee ,  Dong-Ho Lee

IPC: H01L21/00

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5286 ,  H01L24/10 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6627 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an increase in thickness of the package. Further, each pair of rerouting lines on upper and lower rerouted chips includes two or more interconnection bumps. This reduces inductance and resistance of electric signal propagation. Therefore, the multi-chip BGA package of this invention can realize small, thin, high-speed and high-density memory devices.

Abstract translation: 多芯片BGA封装具有两个或更多个重新路由的芯片，每个芯片具有一个或多个电极板。 电极板在重新布线的芯片上与重新路由线共面，并且可以用作去耦电容器，从而降低电源电压波动中的同时开关噪声，而不会增加封装的厚度。 此外，上，下重路由芯片上的每对重新路由线包括两个或多个互连凸块。 这降低了电信号传播的电感和电阻。 因此，本发明的多芯片BGA封装可以实现小型，薄型，高速和高密度的存储器件。

公开(公告)号：US20060170097A1

公开(公告)日：2006-08-03

申请号：US11227161

申请日：2005-09-16

Applicant: Moon-Jung Kim ,  Jong-Joo Lee

Inventor： Moon-Jung Kim ,  Jong-Joo Lee

IPC: H01L23/34

CPC classification number: H05K1/181 ,  G11C5/00 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2224/0401

Abstract: An inline memory module (IMM) architecture may include: a printed circuit board (PCB); a first array of memory devices on a first side of the PCB; a second array of memory devices on a second side of the PCB; at least some of the memory devices of the first array being arranged so as to substantially overlap, relative to a reference axis of the PCB, positional-twin memory devices of the second array, respectively; and multiple vias at least some of which are parts of respective signal paths that connect signal leads of a first memory device in the first array to corresponding signal leads of a second memory device in the second array that is adjacent to a positional-twin third memory device in the second array corresponding to the first memory device.

Abstract translation: 在线存储器模块（IMM）架构可以包括：印刷电路板（PCB）; 在PCB的第一侧上的第一阵列存储器件; 在所述PCB的第二侧上的第二阵列存储器件; 第一阵列的至少一些存储器件被布置成相对于PCB的参考轴线基本上重叠，分别位于第二阵列的位置双存储器件; 以及多个通孔，其中至少一些是将第一阵列中的第一存储器件的信号引线连接到第二阵列中与位置双重第三存储器相邻的第二存储器件的相应信号引线的相应信号路径的部分 第二阵列中的设备对应于第一存储设备。

公开(公告)号：US20060138648A1

公开(公告)日：2006-06-29

申请号：US11305282

申请日：2005-12-16

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC: H01L23/34

CPC classification number: H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

Abstract translation: 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。

公开(公告)号：US07064444B2

公开(公告)日：2006-06-20

申请号：US10828792

申请日：2004-04-20

Applicant: Jong-Joo Lee ,  Dong-Ho Lee

Inventor： Jong-Joo Lee ,  Dong-Ho Lee

IPC: H01L23/48 ,  H01L23/34

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5286 ,  H01L24/10 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6627 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an increase in thickness of the package. Further, each pair of rerouting lines on upper and lower rerouted chips includes two or more interconnection bumps. This reduces inductance and resistance of electric signal propagation. Therefore, the multi-chip BGA package of this invention can realize small, thin, high-speed and high-density memory devices.

Abstract translation: 多芯片BGA封装具有两个或更多个重新路由的芯片，每个芯片具有一个或多个电极板。 电极板在重新布线的芯片上与重新路由线共面，并且可以用作去耦电容器，从而降低电源电压波动中的同时开关噪声，而不会增加封装的厚度。 此外，上，下重路由芯片上的每对重新路由线包括两个或多个互连凸块。 这降低了电信号传播的电感和电阻。 因此，本发明的多芯片BGA封装可以实现小型，薄型，高速和高密度的存储器件。