公开(公告)号：US20060244022A1

公开(公告)日：2006-11-02

申请号：US11170316

申请日：2005-06-30

申请人： Katsuaki Natori ,  Hiroyuki Kanaya ,  Koji Yamakawa

发明人： Katsuaki Natori ,  Hiroyuki Kanaya ,  Koji Yamakawa

IPC分类号： H01L29/00 ,  H01L27/108 ,  H01L21/473

CPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/65

摘要： According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a capacitor which is disposed above the semiconductor substrate and in which a dielectric film is held between lower and upper electrodes, an oxide film formed in such a manner as to coat the capacitor and having a thickness of 5 nm or more and 50 nm or less, and a protective film formed on the oxide film by an ALD process.

公开(公告)号：US20060071258A1

公开(公告)日：2006-04-06

申请号：US10961079

申请日：2004-10-12

申请人： Kazuhiro Tomioka ,  Tomoaki Ishida ,  Masatoshi Fukushima ,  Masanobu Baba ,  Hiroyuki Kanaya ,  Haoren Zhuang

发明人： Kazuhiro Tomioka ,  Tomoaki Ishida ,  Masatoshi Fukushima ,  Masanobu Baba ,  Hiroyuki Kanaya ,  Haoren Zhuang

IPC分类号： H01L29/94

CPC分类号： H01L28/65 ,  H01L21/0334 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L28/55

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a dielectric film provided on the bottom electrode, and a top electrode provided on the dielectric film, a mask film provided on the top electrode and used as a mask when a pattern of the capacitor is formed, wherein an inclination of a side surface of the mask film is gentler than an inclination of a side surface of the top electrode and an inclination of a side surface of the dielectric film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底部电极的电容器，设置在底部电极上的电介质膜和设置在电介质膜上的顶部电极，设置在顶部电极上的掩模膜 并且当形成电容器的图案时用作掩模，其中掩模膜的侧表面的倾斜度比顶部电极的侧表面的倾斜度和电介质膜的侧表面的倾斜度更柔和。

公开(公告)号：US07022531B2

公开(公告)日：2006-04-04

申请号：US10618616

申请日：2003-07-15

申请人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

发明人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

IPC分类号： H01L21/00

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

摘要翻译： 一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。 存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。 多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区 地区。 还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。 第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

公开(公告)号：US20050118795A1

公开(公告)日：2005-06-02

申请号：US10885749

申请日：2004-07-08

申请人： Osamu Hidaka ,  Iwao Kunishima ,  Hiroyuki Kanaya

发明人： Osamu Hidaka ,  Iwao Kunishima ,  Hiroyuki Kanaya

IPC分类号： H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11502 ,  H01L21/76802 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.

摘要翻译： 半导体存储器件包括具有第一区域和第二区域的半导体衬底，放置在半导体衬底的第一区域中的晶体管，在第一和第二区域中的晶体管上形成在半导体衬底上的第一绝缘膜， 形成在第一区域的第一绝缘膜上并与晶体管电连接的第一铁电电容器，形成在第一铁电电容器上方的第一和第二区域上的第一绝缘膜上方的氢阻挡膜， 并且电连接到第一铁电电容器，以及第二触点，其穿过第二区域中的氢阻挡膜并处于浮置状态。

公开(公告)号：US20050002266A1

公开(公告)日：2005-01-06

申请号：US10827331

申请日：2004-04-20

申请人： Hiroyuki Kanaya ,  Iwao Kunishima

发明人： Hiroyuki Kanaya ,  Iwao Kunishima

IPC分类号： H01L21/768 ,  G11C8/02 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11507 ,  H01L28/55

摘要： A semiconductor device includes a switching element formed on a semiconductor substrate, a first interconnect layer formed on the semiconductor substrate and having a first wiring connected to one terminal of the switching element, a ferroelectric capacitor formed on the first interconnect layer and having a first electrode connected to the one terminal of the switching element via the first wiring, a first protective film formed on the ferroelectric capacitor and the first interconnect layer, a second interconnect layer formed on the first protective film and having a second wiring connected to a second electrode of the ferroelectric capacitor and a first interlayer insulating film having a dielectric constant of 4 or more, and a third interconnect layer formed on the second interconnect layer and having a second interlayer insulating film with a dielectric constant of less than 4.

摘要翻译： 半导体器件包括形成在半导体衬底上的开关元件，形成在半导体衬底上并具有连接到开关元件的一个端子的第一布线的第一互连层，形成在第一互连层上并具有第一电极的铁电电容器 通过第一布线连接到开关元件的一个端子，形成在铁电电容器和第一互连层上的第一保护膜，形成在第一保护膜上并具有连接到第二电极的第二布线的第二布线层 铁电电容器和介电常数为4以上的第一层间绝缘膜，以及形成在第二互连层上并具有介电常数小于4的第二层间绝缘膜的第三互连层。

公开(公告)号：US06762065B2

公开(公告)日：2004-07-13

申请号：US10448359

申请日：2003-05-30

申请人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/31116 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/75

摘要： A lower electrode is formed on an insulating film on a semiconductor substrate. A pair of ferroelectric films are formed on the lower electrode separately from each other. An upper electrode is formed on each of the pair of ferroelectric films. A portion of the lower electrode on which the ferroelectric film is formed is thicker than a portion thereof on which the ferroelectric film is not formed. Such a structure is obtained by sequentially depositing the lower electrode, the ferroelectric film, and the upper electrode on the insulating film, forming a mask on the upper-electrode, using this mask to etch the upper-electrode and the ferroelectric film to thereby pattern a pair of upper electrodes and a pair of ferroelectric electrodes, forming such a mask that continuously covers the pair of upper electrodes and the pair of ferroelectric films, and then etching the lower-electrode material film.

摘要翻译： 在半导体衬底上的绝缘膜上形成下电极。 一对铁电体膜分别形成在下电极上。 在一对铁电体膜中的每一个上形成上电极。 形成铁电体膜的下部电极的一部分比不形成强电介质膜的部分厚。 通过使用该掩模在绝缘膜上依次沉积下电极，铁电体膜和上电极，在上电极上形成掩模，以蚀刻上电极和铁电体膜，从而形成图案 一对上电极和一对铁电电极，形成连续地覆盖一对上电极和一对铁电体膜的掩模，然后蚀刻下电极材料膜。

公开(公告)号：US06750093B2

公开(公告)日：2004-06-15

申请号：US10310954

申请日：2002-12-06

申请人： Hiroyuki Kanaya ,  Osamu Hidaka ,  Kumi Okuwada ,  Hiroshi Mochizuki

发明人： Hiroyuki Kanaya ,  Osamu Hidaka ,  Kumi Okuwada ,  Hiroshi Mochizuki

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.

摘要翻译： 半导体集成电路具有铁电电容器。 铁电电容器包括形成在半导体衬底上的第一绝缘膜，第一电极，其被埋在形成在第一绝缘膜中并且其表面平坦化的第一孔中;第二绝缘膜，形成在第一绝缘膜上方，并具有第二绝缘膜 在第二孔中形成的铁电膜，形成在第二孔中并在铁电体膜上方的第二电极，并且与第二绝缘膜的表面齐平。

公开(公告)号：US06680499B2

公开(公告)日：2004-01-20

申请号：US09988138

申请日：2001-11-19

申请人： Yoshinori Kumura ,  Hiroyuki Kanaya ,  Iwao Kunishima

发明人： Yoshinori Kumura ,  Hiroyuki Kanaya ,  Iwao Kunishima

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： Provided are a semiconductor memory device that permits increasing the degree of integration without decreasing the capacitance of the capacitor included in a memory cell, and a method of manufacturing the particular semiconductor memory device. Specifically, provided are a semiconductor memory device, comprising a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first electrode formed on the interlayer insulating film, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, and a third electrode formed on the second ferroelectric film, and a method of manufacturing the particular semiconductor memory device.

摘要翻译： 提供一种允许增加集成度而不减小包括在存储单元中的电容器的电容的半导体存储器件，以及制造特定半导体存储器件的方法。 具体地，提供一种半导体存储器件，包括半导体衬底，形成在半导体衬底上的层间绝缘膜，形成在层间绝缘膜上的第一电极，形成在第一电极上的第一铁电膜，形成在第一电极上的第二电极 第一铁电体膜，形成在第二电极上的第二铁电体膜和形成在第二铁电体膜上的第三电极，以及制造特定半导体存储器件的方法。

公开(公告)号：US06603161B2

公开(公告)日：2003-08-05

申请号：US09801920

申请日：2001-03-09

申请人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L21/31116 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/75

摘要： There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

摘要翻译： 提供一种半导体器件，其具有形成在被绝缘体膜覆盖的半导体衬底上的铁电电容器，其中所述强电介质电容器包括：形成在所述绝缘膜上的底部电极; 形成在底部电极上的铁电体膜; 以及形成在强电介质膜上的顶部电极。 铁电体膜具有两层铁电体膜或三层铁电体膜的层叠结构。 上部铁电膜被金属化，并防止氢在下部铁电层中扩散。 堆叠的铁电体膜的晶粒优选不同。

公开(公告)号：US06190957B1

公开(公告)日：2001-02-20

申请号：US09324501

申请日：1999-06-02

申请人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

发明人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

IPC分类号： H01L218242

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L27/10852 ,  H01L27/11502 ,  H01L28/55

摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成 在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线 电容器接触插头。