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    Semiconductor package with heat sink
    81.
    发明授权
    Semiconductor package with heat sink 有权
    半导体封装带散热片

    公开(公告)号：US06856015B1

    公开(公告)日：2005-02-15

    申请号：US10719726

    申请日：2003-11-21

    Applicant: Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Shih-Kuang Chiu

    Inventor： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Shih-Kuang Chiu

    IPC: H01L21/48 ,  H01L23/367 ,  H01L23/12

    CPC classification number: H01L23/367 ,  H01L21/4882 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/72 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/00012 ,  H01L2924/00015

    Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; at least one chip mounted on the top surface of the substrate and electrically connected to the substrate; a heat sink attached to the top surface of the substrate by an adhesive material applied therebetween; and a plurality of solder balls implanted on the bottom surface of the substrate. The heat sink has a flat portion and a support portion connected to the flat portion. The support portion has at least one recess portion facing toward the top surface of the substrate and at least one burr formed on an interior surface of the recess portion such that the adhesive material can fill the recess portion and submerge the burr to provide an anchoring effect to firmly secure the heat sink in position on the substrate.

    Abstract translation: 半导体封装包括具有顶表面和底表面的衬底; 至少一个芯片安装在所述基板的顶表面上并电连接到所述基板; 通过施加在其之间的粘合剂材料附接到基板的顶表面的散热器; 以及注入到所述基板的底面上的多个焊球。 散热器具有平坦部分和连接到平坦部分的支撑部分。 所述支撑部分具有至少一个面向所述基板的顶表面的凹部和至少一个形成在所述凹部的内表面上的毛刺，使得所述粘合剂材料可以填充所述凹陷部分并浸没所述毛刺以提供锚固效果 以将散热器牢固地固定在基板上的适当位置。

    Semiconductor package with stacked chips
    83.
    发明授权
    Semiconductor package with stacked chips 有权
    半导体封装堆叠芯片

    公开(公告)号：US06541870B1

    公开(公告)日：2003-04-01

    申请号：US09990788

    申请日：2001-11-14

    Applicant: Chien-Ping Huang ,  Tzong-Da Ho ,  cheng-Hsu Hsiao

    Inventor： Chien-Ping Huang ,  Tzong-Da Ho ,  cheng-Hsu Hsiao

    IPC: H01L2348

    CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

    Abstract: A semiconductor package with stacked chips is proposed, wherein at least two chips are stacked on a chip carrier in a stagger manner as to dispose a second chip on a first chip, and a supporting element is disposed on the second chip and dimensioned to cover area on the second chip with no support from the first chip. The supporting element provides support to the second chip, allowing bonding wires to be successfully connected to the second chip, without the occurrence of cracks of the second chip. The supporting element can be formed on its lower surface with protruding portions positioned outside edge sides of the second chip; this is to enhance structural strength of the supporting element, and help maintain the second chip intact in structure during wire bonding. The supporting element can further have its upper surface to be exposed to the atmosphere; this improves heat dissipating efficiency of the semiconductor package.

    Abstract translation: 提出了一种具有堆叠芯片的半导体封装，其中至少两个芯片以错开的方式堆叠在芯片载体上，以将第二芯片布置在第一芯片上，并且支撑元件设置在第二芯片上并且尺寸设置为覆盖区域 在第二个芯片上没有第一个芯片的支持。 支撑元件为第二芯片提供支撑，允许接合线成功地连接到第二芯片，而不会发生第二芯片的裂纹。 支撑元件可以在其下表面上形成有位于第二芯片的边缘侧的突出部分; 这是为了增强支撑元件的结构强度，并且有助于在引线接合期间保持第二芯片的结构完整。 支撑元件还可以使其上表面暴露于大气中; 这提高了半导体封装的散热效率。

    Method for fabricating heat dissipation package structure
    84.
    发明授权
    Method for fabricating heat dissipation package structure 有权
    制造散热封装结构的方法

    公开(公告)号：US08361843B2

    公开(公告)日：2013-01-29

    申请号：US13195617

    申请日：2011-08-01

    Applicant: Min-Shun Hung ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    Inventor： Min-Shun Hung ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    IPC: H01L23/34

    CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/0401 ,  H01L2224/45099

    Abstract: A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip, and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant. Therefore, the heat dissipation package structure is fabricated through simplified fabrication steps at low cost, and also the problem that the chip is easily damaged in a package molding process of the prior art is overcome.

    Abstract translation: 公开了一种散热封装结构及其制造方法，其包括通过其有源表面安装和电连接半导体芯片到芯片载体; 将具有散热部和支撑部的散热部件安装在所述芯片载体上，使得所述半导体芯片能够容纳在由所述散热部和所述支撑部形成的空间中，其中，所述散热部具有相应形成的开口 到半导体芯片; 形成密封剂以封装半导体芯片和散热构件; 并且使所述密封剂变薄以除去形成在所述半导体芯片上的所述密封剂，以从所述密封剂暴露所述半导体芯片的无效表面和所述散热部分的顶表面。 因此，通过以低成本的简化的制造步骤制造散热封装结构，并且克服了在现有技术的封装成型工艺中芯片容易损坏的问题。

    FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE
    85.
    发明申请
    FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE 有权
    多芯片堆叠结构的制作方法

    公开(公告)号：US20100255635A1

    公开(公告)日：2010-10-07

    申请号：US12818701

    申请日：2010-06-18

    Applicant: Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    Inventor： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC: H01L21/60

    CPC classification number: H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    Abstract translation: 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

    Multi-chip stack structure and fabrication method thereof
    86.
    发明授权
    Multi-chip stack structure and fabrication method thereof 有权
    多芯片堆叠结构及其制造方法

    公开(公告)号：US07768106B2

    公开(公告)日：2010-08-03

    申请号：US12077003

    申请日：2008-03-13

    Applicant: Jung-Ping Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    Inventor： Jung-Ping Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC: H01L23/495 ,  H01L21/00

    CPC classification number: H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    Abstract translation: 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

    Semiconductor device package with a heat sink and method for fabricating the same
    90.
    发明授权
    Semiconductor device package with a heat sink and method for fabricating the same 有权
    具有散热器的半导体器件封装及其制造方法

    公开(公告)号：US07485496B2

    公开(公告)日：2009-02-03

    申请号：US11648443

    申请日：2006-12-29

    Applicant: Kun-Sheng Chien ,  Shih-Kuang Chiu ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

    Inventor： Kun-Sheng Chien ,  Shih-Kuang Chiu ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

    IPC: H01L21/00

    CPC classification number: H01L23/3675 ,  H01L21/4871 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251

    Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. A first adhesive of a low Young's modulus is disposed on a corner region of a heat sink mounting area of a substrate. A second adhesive of a high Young's modulus is disposed on the heat sink mounting area except the corner region. The heat sink is mounted on the heat sink mounting area and thereby secured in position to the substrate, by the first and second adhesives. The disposition of the first and second adhesives of different Young's moduli not only prevents detachment of the heat sink from the substrate, but also controls the flatness of the heat sink. The prevent invention does not affect the appearance of the semiconductor package and its ensuing assembly process.

    Abstract translation: 提出了具有散热器的半导体封装及其制造方法。 低杨氏模量的第一粘合剂设置在基板的散热器安装区域的拐角区域。 高杨氏模量的第二粘合剂设置在除了拐角区域之外的散热器安装区域上。 散热器安装在散热器安装区域上，从而通过第一和第二粘合剂固定到基板上。 不同杨氏模量的第一和第二粘合剂的配置不仅防止散热器从基板脱离，而且还控制散热器的平坦度。 防止发明不影响半导体封装的外观及其随后的组装过程。

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