公开(公告)号：US06873050B2

公开(公告)日：2005-03-29

申请号：US09851634

申请日：2001-05-08

Applicant: Alan R. Reinberg

Inventor： Alan R. Reinberg

IPC: H01L21/768 ,  H01L29/34

CPC classification number: H01L21/76865 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76841

Abstract: An intermediate construction of an integrated circuit includes a semiconductive substrate and a raised mandril over the substrate. The raised mandril may be raised out from the substrate and have at least one edge substantially perpendicular to the substrate and at least one beveled edge. A layer of structural material may form an edge defined feature on the at least one perpendicular edge.

Abstract translation: 集成电路的中间结构包括半导体衬底和衬底上的凸起的心轴。 升高的心轴可以从衬底升出并且具有至少一个基本上垂直于衬底的边缘和至少一个倾斜边缘。 一层结构材料可以在至少一个垂直边缘上形成边缘限定特征。

公开(公告)号：US6078066A

公开(公告)日：2000-06-20

申请号：US992907

申请日：1997-12-18

Applicant: Masahiko Akamatsu ,  Fumio Mizohata ,  Mikio Bessho

Inventor： Masahiko Akamatsu ,  Fumio Mizohata ,  Mikio Bessho

IPC: H03K17/00 ,  H01L25/16 ,  H03K17/72 ,  H01L29/744 ,  H01L29/34 ,  H01L29/41

CPC classification number: H01L25/165 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A power semiconductor switching device comprises a mounting board (110) on which a reverse bias driving circuit (20) for applying a reverse bias between the control electrode and one of two main electrodes of a GTO element (11) housed in a flat package is contained. The mounting board (110) has a through hole through which the main electrode of the GTO element (11) penetrates so that the flat package is located in the proximity of the through hole and the perimeter of the through hole partially surrounds the flat package, and a conducting member formed on one surface of the mounting board (110) and electrically connected to the control electrode of the GTO element (11).

Abstract translation: 功率半导体开关器件包括安装板（110），用于在控制电极和容纳在扁平封装中的GTO元件（11）的两个主电极中的一个之间施加反向偏压的反向偏压驱动电路（20） 包含 安装板（110）具有通孔，GTO元件（11）的主电极穿过该通孔，使得扁平封装件位于通孔附近，并且通孔的周边部分地围绕扁平封装， 以及形成在所述安装板（110）的一个表面上并电连接到所述GTO元件（11）的控制电极的导电构件。

公开(公告)号：US6054752A

公开(公告)日：2000-04-25

申请号：US107507

申请日：1998-06-30

Applicant: Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

Inventor： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/34 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/1608

Abstract: A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

Abstract translation: 半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。 在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。 在单电池的周边区域形成沟槽，形成台面结构。 在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。

公开(公告)号：US6051508A

公开(公告)日：2000-04-18

申请号：US145464

申请日：1998-09-02

Applicant: Tamao Takase ,  Tadashi Matsuno ,  Hideshi Miyajima

Inventor： Tamao Takase ,  Tadashi Matsuno ,  Hideshi Miyajima

IPC: H01L21/768 ,  H01L29/34

CPC classification number: H01L21/7681 ,  H01L21/76802 ,  Y10S438/954

Abstract: The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.

Abstract translation: 本发明意图形成多层互连，而不会劣化有机硅氧烷膜（层间电介质）的优点，即低介电常数。 根据本发明，在第一金属层上串联形成有机硅氧烷膜，氮化硅膜，无机SOG膜和光刻胶图案。 然后使用光致抗蚀剂图案作为掩模蚀刻无机SOG膜，以将光致抗蚀剂图案转印到无机SOG膜上。 然后通过使用氮化硅膜作为保护有机硅氧烷膜的保护罩的氧等离子体处理去除光致抗蚀剂图案。 随后，使用无机SOG膜蚀刻氮化硅膜和有机硅氧烷膜，形成到达第一金属层的接触孔。 在去除无机SOG膜之后，形成第二金属层，以通过接触孔与第一金属层接触。

公开(公告)号：US5780891A

公开(公告)日：1998-07-14

申请号：US634118

申请日：1996-04-17

Applicant: Ralph Kauffman ,  Roger Lee

Inventor： Ralph Kauffman ,  Roger Lee

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/34

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/511 ,  Y10S438/954

Abstract: A floating memory device utilizing a composite oxide/oxynitride or oxide/oxynitride/oxide interpoly dielectric.

Abstract translation: 利用复合氧化物/氧氮化物或氧化物/氧氮化物/氧化物层间电介质的浮动存储器件。

公开(公告)号：US5773362A

公开(公告)日：1998-06-30

申请号：US838539

申请日：1997-04-09

Applicant: William R. Tonti ,  Jack A. Mandelman ,  Jerzy M. Zalesinski ,  Toshiharu Furukawa ,  Son V. Nguyen ,  Dureseti Chidambarrao

Inventor： William R. Tonti ,  Jack A. Mandelman ,  Jerzy M. Zalesinski ,  Toshiharu Furukawa ,  Son V. Nguyen ,  Dureseti Chidambarrao

IPC: H01L21/60 ,  H01L23/367 ,  H01L29/06 ,  H01L29/34 ,  H01L21/44

CPC classification number: H01L24/27 ,  H01L23/367 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/34 ,  H01L2224/03505 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32057 ,  H01L2224/32059 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/181 ,  Y10S438/928 ,  Y10S438/964

Abstract: A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips. The heatsink itself is prepared by first optionally roughening the surface and metalizing the backside of the heatsink with metal interlayer. Next, the chip is thermally attached to the heatsink by reflowing the thermally conductive reflowable material.

Abstract translation: 简单且低成本的ULSI集成散热器通过将散热材料集成到硅晶片中更有效地从硅封装中去除热量，将现有的二维技术转化为三维。 高功率集成ULSI封装和散热器的制造开始于制造集成电路晶片，直到将晶片切割成单个芯片。 晶片的正面受到保护，而晶片的背面露出。 暴露的背面通过化学和/或机械过程粗糙化。 任选地，然后执行吸气过程以除去杂质。 然后用金属夹层涂覆粗糙的背面，优选用铬（Cr）形成铝（Al）。 一层铜（Cu）任选地涂覆在金属夹层上。 高度导电的可回流材料，例如焊料或金共晶，沉积在金属夹层上。 此时，晶片被切割成芯片。 散热器本身通过首先任选地使表面粗糙化并用金属中间层金属化散热器的背面来制备。 接下来，通过回流导热的可回流材料将芯片热连接到散热器。

公开(公告)号：US5710461A

公开(公告)日：1998-01-20

申请号：US781429

申请日：1997-01-10

Applicant: Loi Nguyen ,  Ravishankar Sundaresan

Inventor： Loi Nguyen ,  Ravishankar Sundaresan

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/8244 ,  H01L29/34 ,  H01L23/48 ,  H01L23/522 ,  H01L29/54

CPC classification number: H01L21/76819 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

公开(公告)号：US5698894A

公开(公告)日：1997-12-16

申请号：US738738

申请日：1996-10-28

Applicant: Frank Randolph Bryant ,  Abha Rani Singh

Inventor： Frank Randolph Bryant ,  Abha Rani Singh

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/525 ,  H01L29/34

CPC classification number: H01L22/20 ,  H01L23/3171 ,  H01L23/5258 ,  H01L2924/0002 ,  Y10S438/958

Abstract: A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging.

Abstract translation: 使用两个钝化层和使用两个掩蔽步骤的保护性外涂层形成钝化结构。 第一钝化层形成在晶片之上，并且提供开口以暴露焊盘的部分以测试设备和可熔链路。 在测试和激光修复之后，在晶片上形成第二钝化层，然后沉积保护外涂层。 保护性外涂层被图案化和蚀刻，露出垫。 保护性外涂层的其余部分用作掩模以去除覆盖在焊盘上的第二钝化层的部分。 引线然后连接到焊盘，并且器件被封装以进行封装。

公开(公告)号：US5539257A

公开(公告)日：1996-07-23

申请号：US456942

申请日：1995-06-01

Applicant: Yuji Hara ,  Satoru Ito ,  Tatsuro Toya

Inventor： Yuji Hara ,  Satoru Ito ,  Tatsuro Toya

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/58 ,  H01L27/02 ,  H01L23/48 ,  H01L29/34 ,  H01L29/44

CPC classification number: H01L23/3171 ,  H01L23/291 ,  H01L23/585 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

公开(公告)号：US5502668A

公开(公告)日：1996-03-26

申请号：US201730

申请日：1994-02-25

Applicant: Noriyuki Shimoji ,  Hidemi Takasu

Inventor： Noriyuki Shimoji ,  Hidemi Takasu

IPC: H01L29/34 ,  H01L29/788 ,  H01L29/68

CPC classification number: H01L29/34 ,  H01L29/7883

Abstract: A poly-silicon or amorphous silicon plate having cone-like protrusions is provided on a Si substrate in a tunnel window area such that the edges of the protrusions are placed very close to a floating gate. Alternatively, the top surface of a Si substrate is shaped into protrusions.

Abstract translation: 在隧道窗口区域中的Si衬底上提供具有锥形突起的多晶硅或非晶硅板，使得突起的边缘非常靠近浮动栅极。 或者，Si衬底的顶表面成形为突起。