公开(公告)号：US08143117B2

公开(公告)日：2012-03-27

申请号：US12539614

申请日：2009-08-12

申请人： Ming-Wei Sun ,  Chen-Yueh Li ,  Yu-Cheng Chen ,  Chia-Tien Peng

发明人： Ming-Wei Sun ,  Chen-Yueh Li ,  Yu-Cheng Chen ,  Chia-Tien Peng

IPC分类号： H01L21/336 ,  H01L21/8232 ,  H01L27/085

CPC分类号： H01L27/14692 ,  H01L27/1214 ,  H01L27/1288 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14645

摘要： A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

摘要翻译： 提供一种用于制造有源器件阵列衬底的方法。 第一图案化半导体层，栅极绝缘体，第一图案化导电层和第一介电层依次形成在衬底上。 暴露第一图案化半导体层的第一接触孔形成在第一介电层和栅极绝缘体中。 第一图案化导电层和设置在其上的第二图案化半导体层同时形成在第一介电层上。 第二导电层包括接触导体和底部电极。 第二图案化半导体层包括有源层。 具有第二接触孔的第二电介质层形成在第一电介质层上，其中一部分第二接触孔露出有源层。 通过第二接触孔的一部分电连接到有源层的第三图案化导电层形成在第二介电层上。

公开(公告)号：US08110853B2

公开(公告)日：2012-02-07

申请号：US12475661

申请日：2009-06-01

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L27/085

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor.

摘要翻译： 半导体结构。 半导体结构包括半导体衬底，半导体衬底上的第一晶体管和半导体衬底上的保护环。 半导体衬底包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面。 保护环包括掺杂有掺杂极性的半导体材料。 在参考方向上第一晶体管的第一掺杂晶体管区域和参考方向上的保护环的第一掺杂保护环区域的第二掺杂分布的第一掺杂分布基本上是相同的掺杂分布。 保护环围绕第一晶体管形成闭环。

公开(公告)号：US20110303953A1

公开(公告)日：2011-12-15

申请号：US13154692

申请日：2011-06-07

申请人： Koichiro KAMATA

发明人： Koichiro KAMATA

IPC分类号： H01L27/085 ,  H01L21/8232

CPC分类号： G01N27/4141 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/66969

摘要： It is an object to provide a gas sensor which is formed by a simple manufacturing process. Another object is to provide a gas sensor whose manufacturing cost is reduced. A transistor which includes an oxide semiconductor layer in contact with a gas and which serves as a detector element of a gas sensor, and a transistor which includes an oxide semiconductor layer in contact with a film having a gas barrier property and which forms a detection circuit are formed over one substrate by the same process, whereby a gas sensor using these transistors may be formed.

摘要翻译： 本发明的目的是提供一种通过简单的制造工艺形成的气体传感器。 另一个目的是提供一种制造成本降低的气体传感器。 一种晶体管，包括与气体接触并用作气体传感器的检测器元件的氧化物半导体层，以及晶体管，其包括与具有阻气性的膜接触的氧化物半导体层，并形成检测电路 通过相同的工艺形成在一个衬底上，由此可以形成使用这些晶体管的气体传感器。

公开(公告)号：US20110220973A1

公开(公告)日：2011-09-15

申请号：US12795486

申请日：2010-06-07

申请人： Chih-Min HU ,  Chung Yu HUNG ,  Wing Chor CHAN ,  Jeng GONG

发明人： Chih-Min HU ,  Chung Yu HUNG ,  Wing Chor CHAN ,  Jeng GONG

IPC分类号： H01L27/085

CPC分类号： H01L29/66901 ,  H01L29/808

摘要： A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.

摘要翻译： 结场效应晶体管（JFET）器件包括第一类杂质的衬底，衬底中第二类杂质的第一阱区，第一类杂质的一对第二阱区与 在第一阱区域中彼此相对的第一阱区域，第一阱区域之间的第一类型杂质的第三阱区域，第三阱区域和第二阱区域之一中的第二类型杂质的第一扩散区域，以及 在第三阱区域和第二阱区域中的另一个区域之间的第二类型杂质的第二扩散区域。

公开(公告)号：US20110121883A1

公开(公告)日：2011-05-26

申请号：US12623655

申请日：2009-11-23

申请人： John V. VELIADIS

发明人： John V. VELIADIS

IPC分类号： H03K17/687 ,  H01L27/085

CPC分类号： H01L27/098 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/8083 ,  H03K17/102

摘要： A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (D1 and D2), and a source, and have gate-to-drain and gate-to-source built-in potentials. The first VJFET and the second VJFET are connected back-to-back in series so that the sources of each are shorted together at a common point S. The gate drive applies an equal voltage bias (VG) to both the gates. The gate drive is configured to selectively bias VG so that current flows through the VJFETs in the D1 to D2 direction, flows through the VJFETs in the D2 to D1 direction or voltages applied to D1 of the first VJFET or D2 of the second VJFET are blocked.

摘要翻译： 一种用于为高压应用提供对称，高效的双向功率流和功率调节的系统和方法。 实施例包括第一垂直沟道结栅场效应晶体管（VJFET），第二VJFET，耦合到第一VJFET栅极和第二VJFET栅极的栅极驱动。 两个VJFET包括栅极，漏极（D1和D2）和源极，并具有栅极到漏极和栅极到源极的内置电位。 第一VJFET和第二VJFET串联背对背地连接，使得每个源的源在公共点S短路在一起。栅极驱动对两个栅极施加相等的电压偏置（VG）。 栅极驱动器被配置为选择性地偏置VG，使得电流在D1至D2方向上流过VJFET，在D2至D1方向上流过VJFET，或者施加到第一VJFET的D1或第二VJFET的D2的电压被阻挡 。

公开(公告)号：US20110108850A1

公开(公告)日：2011-05-12

申请号：US12914930

申请日：2010-10-28

申请人： Kai CHENG ,  Stefan Degroote

发明人： Kai CHENG ,  Stefan Degroote

IPC分类号： H01L27/085 ,  H01L21/8232

CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L21/8258

摘要： An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.

摘要翻译： 公开了一种集成半导体衬底结构。 一方面，该结构包括衬底，GaN异质结构和半导体衬底层。 GaN异质结构存在于用于GaN基器件的定义的第一器件区域中，并且至少部分地被保护层覆盖。 半导体衬底层存在于用于CMOS器件定义的第二器件区域中。 至少GaN基异质结构和半导体衬底层中的至少一个设置在衬底中的至少一个沟槽中，使得GaN异质结构和半导体衬底层横向并置。

公开(公告)号：US07906383B2

公开(公告)日：2011-03-15

申请号：US12045095

申请日：2008-03-10

申请人： Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

发明人： Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

IPC分类号： H01L21/8238 ,  H01L21/311 ,  H01L21/70 ,  H01L27/085

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

摘要： By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.

摘要翻译： 通过在不同的晶体管上形成应力介电层并随后放松其一部分，可以增强用于通过应力覆盖层在晶体管的沟道区域中产生应变的方法中的整体工艺效率，同时可以为每种类型的晶体管获得晶体管性能增益 由于位于先前松弛部分之上的高应力材料也可有效地影响底层晶体管。

公开(公告)号：US20110024798A1

公开(公告)日：2011-02-03

申请号：US12805160

申请日：2010-07-15

申请人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

发明人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

IPC分类号： H01L27/085 ,  H01L21/8238 ,  H01L21/335 ,  H01L29/778

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/098 ,  H01L29/205 ,  H01L29/66462

摘要： A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer.

摘要翻译： 半导体器件包括：化合物半导体衬底; 形成在所述化合物半导体衬底上并且包括第一沟道层的n沟道场效应晶体管区; n型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供n型电荷; 以及对n型第一阻挡层具有pn结型势垒的p型栅极区域; 以及形成在化合物半导体衬底上的p沟道场效应晶体管区，并且包括p型第二沟道层和对p型第二沟道pn结型势垒的n型栅极区 通道层。

公开(公告)号：US07821035B2

公开(公告)日：2010-10-26

申请号：US12325784

申请日：2008-12-01

申请人： Takehiko Nomura ,  Hiroshi Kambayashi ,  Yuki Niiyama ,  Seikoh Yoshida

发明人： Takehiko Nomura ,  Hiroshi Kambayashi ,  Yuki Niiyama ,  Seikoh Yoshida

IPC分类号： H01L27/085

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/86 ,  H01L27/0605 ,  H01L29/2003 ,  H03K3/0315

摘要： A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first source electrode and a first drain electrode formed across a first gate electrode make an ohmic contact to the second semiconductor layer. A second source electrode and a second drain electrode formed across a second gate electrode that makes a Schottky contact to the second semiconductor layer make an ohmic contact to the second semiconductor layer.

摘要翻译： 在具有较小带隙的第一氮化物基化合物半导体的第一半导体层上形成的具有较宽带隙的第二氮化物基化合物半导体的第二半导体层包括开口，在其上形成栅绝缘层 通过开放。 在第一栅极电极上形成的第一源电极和第一漏电极与第二半导体层形成欧姆接触。 形成在与第二半导体层形成肖特基接触的第二栅电极上的第二源极和第二漏极与第二半导体层形成欧姆接触。

公开(公告)号：US20100264466A1

公开(公告)日：2010-10-21

申请号：US12825580

申请日：2010-06-29

申请人： Xiaoju Wu ,  Fan-Chi Frank Hou ,  Pinghai Hao

发明人： Xiaoju Wu ,  Fan-Chi Frank Hou ,  Pinghai Hao

IPC分类号： H01L27/085 ,  H01L29/80

CPC分类号： H01L29/808 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/66901

摘要： The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

摘要翻译： 本文的公开内容涉及形成低噪声结场效应晶体管（JFET），其中晶体管栅极材料用于形成和电隔离JFET的有源区。 更具体地，有源区域与图案化的栅极电极材料和侧壁间隔物自对准，其有助于期望将有源区域定位在半导体衬底中。 这减轻了在衬底中需要额外的材料以将有源区彼此隔离，其中这些附加材料可以将噪声引入到JFET中。 这也允许一层栅极电介质材料保留在衬底的表面上，其中栅极介电材料层在衬底的表面处提供基本上均匀的界面，其有助于活性区域之间的不受限制的电流流动，从而促进期望的 设备操作。