Abstract:
A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth beam adjusting elements; a first, a second, a third, and a fourth beam control modules; a first, a second, a third, and a fourth radiation strips positioned within an area surrounded by the first to eighth beam adjusting elements; and a radiation strip control module for selecting either the first and second radiation strips or the third and fourth radiation strips to transmit signals. When the first beam control module conducts the first and second beam adjusting elements, the third beam control module does not conduct the fifth and sixth beam adjusting elements. When the second beam control module conducts the third and fourth beam adjusting elements, the fourth beam control module does not conduct the seventh and eighth beam adjusting elements.
Abstract:
An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.
Abstract:
A computer managing method includes the following steps. Firstly, a blade server system with M blade server units, which includes a number of server blades and a modular management blade (MMB), is provided, wherein the M MMBs are connected with each other via network paths and M is a natural number greater than 1. Then a master MMB among the M MMBs are selected in response to first user operation event. Next, the network parameter data of the master MMB are set in response to second user operation event. Then network topology of the master MMB and the rest of M−1 MMBs are obtained via the master MMB. After that, the rest of M−1 MMBs are driven for utilizing a network protocol service so that the M−1 MMBs are able to receive network parameter data from the master MMB and carry out parameter setting accordingly.
Abstract:
A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth beam adjusting elements; a first, a second, a third, and a fourth beam control modules; a first, a second, a third, and a fourth radiation strips positioned within an area surrounded by the first to eighth beam adjusting elements; and a radiation strip control module for selecting either the first and second radiation strips or the third and fourth radiation strips to transmit signals. When the first beam control module conducts the first and second beam adjusting elements, the third beam control module does not conduct the fifth and sixth beam adjusting elements. When the second beam control module conducts the third and fourth beam adjusting elements, the fourth beam control module does not conduct the seventh and eighth beam adjusting elements.
Abstract:
A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.
Abstract:
A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.
Abstract:
A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.
Abstract:
A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.
Abstract:
An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.
Abstract:
An operation method for a server system includes: (A) under control of a hardware abstraction layer (HAL), a plurality of node management units sharing a hardware resource; (B) if one of the node management units needs to use the hardware resource, the node management unit sending an instruction or a data to the HAL and accordingly the HAL using the hardware resource in represent of the node management unit; and (C) if an external instruction is received, the HAL identifying which transmission port of the hardware resource receives the external instruction, so to send the external instruction to a corresponding node management unit, and after the external instruction is executed, the corresponding node management unit sending back an information to the HAL so that the HAL sends back the information to an external system administrator.