公开(公告)号：US20110108850A1

公开(公告)日：2011-05-12

申请号：US12914930

申请日：2010-10-28

申请人： Kai CHENG ,  Stefan Degroote

发明人： Kai CHENG ,  Stefan Degroote

IPC分类号： H01L27/085 ,  H01L21/8232

CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L21/8258

摘要： An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.

摘要翻译： 公开了一种集成半导体衬底结构。 一方面，该结构包括衬底，GaN异质结构和半导体衬底层。 GaN异质结构存在于用于GaN基器件的定义的第一器件区域中，并且至少部分地被保护层覆盖。 半导体衬底层存在于用于CMOS器件定义的第二器件区域中。 至少GaN基异质结构和半导体衬底层中的至少一个设置在衬底中的至少一个沟槽中，使得GaN异质结构和半导体衬底层横向并置。

公开(公告)号：US20150006834A1

公开(公告)日：2015-01-01

申请号：US13931875

申请日：2013-06-29

申请人： Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

发明人： Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

IPC分类号： G06F3/06

CPC分类号： G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

摘要： An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

摘要翻译： 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

公开(公告)号：US20130001507A1

公开(公告)日：2013-01-03

申请号：US13438718

申请日：2012-04-03

申请人： Kai CHENG ,  Matty Caymax

发明人： Kai CHENG ,  Matty Caymax

IPC分类号： H01L29/06 ,  H01L29/02 ,  H01L21/20

CPC分类号： H01L21/02494 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02587 ,  H01L33/007 ,  H01L33/06

摘要： A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.

摘要翻译： 公开了一种半导体器件及其制造方法。 在一个方面，一种方法包括提供衬底，在衬底的顶部上提供第一外延半导体层，并形成一维或二维重复图案，该图案的每一部分具有在约0.1范围内的纵横比 到50。