公开(公告)号：US20190189466A1

公开(公告)日：2019-06-20

申请号：US16270624

申请日：2019-02-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Jintyou ,  Junichi Koezuka ,  Takashi Hamochi ,  Yasuharu Hosaka

IPC: H01L21/385 ,  H01L21/02 ,  H01L21/44 ,  H01L21/443 ,  H01L29/786 ,  H01L29/04 ,  H01L29/49 ,  H01L29/66 ,  H01L21/4757

CPC classification number: H01L21/385 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/44 ,  H01L21/443 ,  H01L21/4757 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

公开(公告)号：US10304792B1

公开(公告)日：2019-05-28

申请号：US15814736

申请日：2017-11-16

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Hongying Zhang ,  HongLiang Cai

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768

Abstract: A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.

公开(公告)号：US20190131267A1

公开(公告)日：2019-05-02

申请号：US15796091

申请日：2017-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHUEI-TANG WANG ,  CHIH-CHIEH CHANG ,  YU-KUANG LIAO ,  HSING-KUO HSIA ,  CHIH-YUAN CHANG ,  JENG-SHIEN HSIEH ,  CHEN-HUA YU

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.

公开(公告)号：US10276400B2

公开(公告)日：2019-04-30

申请号：US15022283

申请日：2015-09-18

Applicant: Boe Technology Group Co., Ltd.

Inventor： Seongyeol Yoo ,  Seungjin Choi ,  Youngsuk Song

IPC: H01L21/44 ,  H01L27/12 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: The invention relates to a method for fabricating an array substrate, an array substrate and a display device. The method for fabricating an array substrate may comprise: forming a pattern including a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer; and performing annealing, so as to convert only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line to a metal semiconductor compound. By converting only the non-crystalline semiconductor thin film layer on the source electrode, drain electrode and data line into a metal semiconductor compound, the resulting metal semiconductor compound may prevent oxidative-corrosion of the metal thin film layer, such as a low-resistance metal (e.g., Cu or Ti) layer, in the subsequent procedures, which is favorable for the fabrication of a metal oxide thin film transistor using Cu or Ti.

公开(公告)号：US10269757B2

公开(公告)日：2019-04-23

申请号：US14989181

申请日：2016-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Tien-I Bao

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

Abstract: An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.

公开(公告)号：US10263109B2

公开(公告)日：2019-04-16

申请号：US14995215

申请日：2016-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L21/8234 ,  H01L21/44 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US10262951B2

公开(公告)日：2019-04-16

申请号：US14279601

申请日：2014-05-16

Applicant: Jin Ho Kang ,  Godfrey Sauti ,  Cheol Park ,  Luke Gibbons ,  Sheila Ann Thibeault ,  Sharon E. Lowther ,  Robert G. Bryant

Inventor： Jin Ho Kang ,  Godfrey Sauti ,  Cheol Park ,  Luke Gibbons ,  Sheila Ann Thibeault ,  Sharon E. Lowther ,  Robert G. Bryant

IPC: H01L21/44 ,  H01L23/556 ,  H01L23/552 ,  H01L21/78 ,  H01L23/31 ,  H01L21/311 ,  H01L23/495 ,  H01L23/00

Abstract: A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation.

公开(公告)号：US10262922B2

公开(公告)日：2019-04-16

申请号：US15910136

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L23/46 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683

Abstract: Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

公开(公告)号：US10256201B2

公开(公告)日：2019-04-09

申请号：US15797956

申请日：2017-10-30

Applicant: Vanguard International Semiconductor Corporation

Inventor： Chi-Li Tu ,  Hung-Wei Chen ,  Shi-Hsiang Lu ,  Ching-Wen Wang

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

公开(公告)号：US10242879B2

公开(公告)日：2019-03-26

申请号：US15492976

申请日：2017-04-20

Applicant: Lam Research Corporation

Inventor： Jeong-Seok Na ,  Raashina Humayun

IPC: H01L21/44 ,  H01L21/285 ,  H01L21/768 ,  C23C16/52 ,  C23C16/455

Abstract: Provided herein are atomic layer deposition (ALD) methods of depositing cobalt in a feature. The methods involve two-step surface treatments during an ALD cycle, with one step involving the reaction of a co-reactant gas with an adsorbed cobalt precursor and the other step involving a growth-inhibiting reactant gas on the cobalt surface. The growth-inhibiting reactant gas significantly lowers cobalt growth rate, producing a highly conformal cobalt film. The described ALD processes enable improved controllability in film nucleation, step coverage, and morphology by the separate surface treatment and low process temperature. The methods are applicable to a variety of feature fill applications including the fabrication of metal gate/contact fill in front end of line (FEOL) processes as well as via/line fill in back end of line (BEOL) processes.