摘要:
In one embodiment, the present invention includes a method for associating a first plurality of current sources with a first tap coefficient and associating a second plurality of current sources with a second tap coefficient. A first plurality of output switches coupled to the first plurality of current sources is gated using the first tap coefficient and a second plurality of output switches coupled to the second plurality of current sources is gated using the second tap coefficient. In such manner, the first and second plurality of equalized current sources may be driven onto an interconnect. Other embodiments are described and claimed.
摘要:
An output driver is disclosed. The output driver has a pair of differential outputs coupled to a first supply voltage via a pair of load devices and comprises a current source, a pair of low voltage transistors, a pair of high voltage transistors, and a resistor. The current source has one end coupled to a second supply voltage. Each of the low voltage transistors has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage signal, and a third terminal. Each of the high voltage transistors has a first terminal coupled to the third terminal of a corresponding one of the low voltage transistors, a second terminal coupled to a bias voltage and a third terminal coupled to the output. The resistor is connected between the third terminals of the high voltage transistors.
摘要:
A low power differential signaling transmitter includes a switchable current source apparatus and a differential signaling generator coupled to the switchable current source apparatus. The switchable current source apparatus receives a first input voltage and a second input voltage, and generates a plurality of reference currents according to the first input voltage and the second input voltage. The differential signaling generator includes a plurality of first transistors, a plurality of second transistors, a first output voltage terminal and a second output voltage terminal. The on or off states of the first transistors and the second transistors are controlled by the reference currents. The first output voltage terminal outputs a first output voltage, and the second output voltage terminal outputs a second output voltage. The first output voltage and the second output voltage are determined according to the on or off states of the first and second transistors.
摘要:
Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.
摘要:
A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device.
摘要:
Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.
摘要:
A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.
摘要:
A signal transmission apparatus may transmit and receive a differential signal using transmission lines. The apparatus may include a transmitter and a receiver. The transmitter may transmit a mixed signal obtained by mixing the differential signal with a single ended signal. The receiver may restore the differential signal and the single ended signal from the mixed signal. An edge of the single ended signal may have a phase difference of about 90° with an edge of the differential signal. The signal transmission apparatus and method may transmit two signals through a single channel to reduce a circuit area.
摘要:
A buffer circuit device, which receives differential input signals and outputs differential output signals, has a buffer circuit, a common mode level generator circuit, a common mode voltage detection circuit, and a bias voltage adjusting circuit. The buffer circuit receives the input signals and outputs the output signals, and the common mode level generator circuit outputs a specific level of a common mode voltage of the output signals to be output from the buffer circuit. The common mode voltage detection circuit detects a common mode voltage of specific signals, and the bias voltage adjusting circuit adjusts a bias voltage to be supplied to the buffer circuit by comparing an output signal of the common mode level generator circuit with an output signal of the common mode voltage detection circuit.
摘要:
An apparatus and method for simultaneously transmitting a digital control signal and an analog signal from a sending circuit to a receiving circuit are described. An analog signal (e.g., a differential data signal) is received. A digital signal (e.g., a digital logic signal) is also received. The digital signal is then combined with the analog signal to generate an analog signal with an embedded digital signal. The analog signal with an embedded digital signal is then transmitted through a common communication link (e.g., a pair of conductors). The digital signal is then recovered from the analog signal with an embedded digital signal without affecting the recovery of the analog signal.