公开(公告)号：US08648349B2

公开(公告)日：2014-02-11

申请号：US13121122

申请日：2010-05-12

申请人： Takeyoshi Masuda ,  Misako Honaga

发明人： Takeyoshi Masuda ,  Misako Honaga

IPC分类号： H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66909 ,  H01L29/8083

摘要： A MOSFET which is a semiconductor device capable of achieving a stable reverse breakdown voltage and reduced on-resistance includes a SiC wafer of an n conductivity type, a plurality of p bodies of a p conductivity type formed to include a first main surface of the SiC wafer, and n+ source regions of the n conductivity type formed in regions surrounded by the plurality of p bodies, respectively, when viewed two-dimensionally. Each of the p bodies has a circular shape when viewed two-dimensionally, and each of the n+ source regions is arranged concentrically with each of the p bodies and has a circular shape when viewed two-dimensionally. Each of the plurality of p bodies is arranged to be positioned at a vertex of a regular hexagon when viewed two-dimensionally.

摘要翻译： 作为能够实现稳定的反向击穿电压和降低的导通电阻的半导体器件的MOSFET包括n导电型的SiC晶片，形成为包括SiC晶片的第一主表面的多个p导电类型的多个p体 ，以及分别形成在由多个p体包围的区域中的n导电类型的n +源极区域。 每个p体在二维观察时具有圆形形状，并且n +源区域中的每一个与每个p体同心地布置，并且在二维观察时具有圆形形状。 当二维观察时，多个p体中的每一个被布置成定位在正六边形的顶点处。

公开(公告)号：US20130240981A1

公开(公告)日：2013-09-19

申请号：US13867215

申请日：2013-04-22

申请人： INFINEON TECHNOLOGIES AUSTRIA AG

发明人： Michael HUTZLER ,  Hans-Joachim SCHULZE ,  Ralf SIEMIENIEC

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/8083

摘要： Disclosed are a semiconductor device and a method for producing a semiconductor device. A MOSFET may have a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type disposed between the source region and the drift region, and a gate electrode disposed adjacent to said body region. The gate electrode may be isolated from the body region by a dielectric, and have a source electrode contacting the source region and the body region. A self-locking JFET, associated with the MOSFET, may have a channel region of the first conductivity type, the channel region connected between the source electrode and the drift region, and coupled to and adjacent the body region.

摘要翻译： 公开了半导体器件和半导体器件的制造方法。 MOSFET可以具有源区域，漂移区域和第一导电类型的漏极区域，设置在源极区域和漂移区域之间的第二导电类型的体区域，以及邻近所述体区域设置的栅极电极。 栅电极可以通过电介质与体区隔离，并且具有与源区和身体区接触的源电极。 与MOSFET相关联的自锁JFET可以具有第一导电类型的沟道区域，沟道区域连接在源电极和漂移区域之间，并且耦合到身体区域并邻近身体区域。

公开(公告)号：US20130221430A1

公开(公告)日：2013-08-29

申请号：US13594837

申请日：2012-08-26

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US08513675B2

公开(公告)日：2013-08-20

申请号：US13476304

申请日：2012-05-21

申请人： David C. Sheridan ,  Andrew P. Ritenour

发明人： David C. Sheridan ,  Andrew P. Ritenour

IPC分类号： H01L29/24 ,  H01L49/00

CPC分类号： H01L29/8083 ,  H01L21/047 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068

摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）。 这些装置具有向内倾斜的具有倾斜侧壁的凸起区域。 侧壁可以垂直于基板表面形成5°或更大的角度。 这些装置可以具有双斜面侧壁，其中侧壁的下部形成垂直方向为5°或更大的角度，并且侧壁的上部部分与垂直方向形成<5°的角度。 可以使用正常（即0°）或接近正常的入射离子注入来制造器件。 这些器件具有相对均匀的侧壁掺杂，并且可以在没有成角度注入的情况下制造。

公开(公告)号：US20130164893A1

公开(公告)日：2013-06-27

申请号：US13335355

申请日：2011-12-22

申请人： Linda Romano ,  David P. Bour ,  Andrew Edwards ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown ,  Thomas R. Prunty

发明人： Linda Romano ,  David P. Bour ,  Andrew Edwards ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L21/337 ,  H01L21/20

CPC分类号： H01L29/0619 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

摘要： A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate.

摘要翻译： 一种用于制造氮化镓（GaN）材料中的边缘端接结构的方法包括提供具有第一表面和第二表面的n型GaN衬底，形成耦合到n型GaN的第一表面的n型GaN外延层 并且形成耦合到n型GaN外延层的生长掩模。 该方法进一步包括图案化生长掩模以暴露n型GaN外延层的至少一部分，以及形成耦合到n型GaN外延层的至少一部分的至少一个p型GaN外延结构。 所述至少一个p型GaN外延结构包括边缘端接结构的至少一部分。 该方法还包括形成电耦合到n型GaN衬底的第二表面的第一金属结构。

公开(公告)号：US20130153917A1

公开(公告)日：2013-06-20

申请号：US13326192

申请日：2011-12-14

申请人： Linda Romano ,  Andrew Edwards ,  Dave P. Bour ,  Isik C. Kizilyalli

发明人： Linda Romano ,  Andrew Edwards ,  Dave P. Bour ,  Isik C. Kizilyalli

IPC分类号： H01L29/20 ,  H01L21/332 ,  H01L21/20

CPC分类号： H01L29/66916 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/452 ,  H01L29/66924 ,  H01L29/8083

摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

公开(公告)号：US20130087835A1

公开(公告)日：2013-04-11

申请号：US13270606

申请日：2011-10-11

申请人： Andrew Edwards ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

发明人： Andrew Edwards ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC分类号： H01L29/808 ,  H01L21/20 ,  H01L21/337

CPC分类号： H01L29/66143 ,  H01L21/26546 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66083 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/66416 ,  H01L29/66924 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure further includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, a first metallic structure electrically coupled to the second surface of the III-nitride substrate, and a III-nitride epitaxial structure of a second conductivity type coupled to the III-nitride epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

摘要翻译： 半导体结构包括具有第一侧和与第一侧相对的第二侧的III族氮化物衬底。 III族氮化物衬底的特征在于第一导电类型和第一掺杂剂浓度。 半导体结构还包括耦合到III族氮化物衬底的第一表面的第一导电类型的III族氮化物外延层，电耦合到III族氮化物衬底的第二表面的第一金属结构和III族氮化物 耦合到III族氮化物外延层的第二导电类型的外延结构。 III族氮化物外延结构包括至少一个边缘端接结构。

公开(公告)号：US08395163B2

公开(公告)日：2013-03-12

申请号：US12937435

申请日：2009-04-13

申请人： Hideto Tamaso

发明人： Hideto Tamaso

IPC分类号： H01L29/15 ,  H01L27/15

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/8083

摘要： A MOSFET capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration includes an SiC wafer composed of silicon carbide and a source contact electrode arranged in contact with the SiC wafer and containing titanium, aluminum, silicon, and carbon as well as a remaining inevitable impurity. The SiC wafer includes an n+ source region having an n conductivity type and a p+ region having a p conductivity type. Both of the n+ source region and the p+ region are in contact with the source contact electrode. The source contact electrode contains aluminum and titanium in a region including an interface with the SiC wafer.

摘要翻译： 能够实现制造工序中的台阶数减少和集成化的改善的MOSFET包括由碳化硅构成的SiC晶片和与SiC晶片接触并且包含钛，铝，硅和碳的源极接触电极， 以及剩下的不可避免的杂质。 SiC晶片包括具有n导电类型的n +源区和具有p导电类型的p +区。 n +源极区域和p +区域都与源极接触电极接触。 源极接触电极在包括与SiC晶片的界面的区域中包含铝和钛。

公开(公告)号：US08390362B2

公开(公告)日：2013-03-05

申请号：US12853631

申请日：2010-08-10

申请人： Mario Motz

发明人： Mario Motz

IPC分类号： G05F3/02

CPC分类号： H01L23/62 ,  H01L27/0251 ,  H01L29/8083 ,  H01L29/872 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

摘要： Embodiments relate to an ultra-low-power, high-voltage integrated circuit (IC) that also has high electromagnetic compatibility (EMC). Embodiments address the desire for an ultra-low-power, high-voltage IC that also has high EMC and comprise a high-voltage EMC protection circuit with normal current consumption coupled to an ultra-low-power, low-voltage oscillator that controls a sleep/wake, or duty, cycle of a high-voltage circuit.

摘要翻译： 实施例涉及也具有高电磁兼容性（EMC）的超低功率高压集成电路（IC）。 实施例解决了对具有高EMC的超低功率高电压IC的需求，并且包括具有正常电流消耗的高电压EMC保护电路，其耦合到超低功率，低压振荡器，其控制 睡眠/唤醒或占空比，高压电路的周期。

公开(公告)号：US20130032814A1

公开(公告)日：2013-02-07

申请号：US13198666

申请日：2011-08-04

申请人： David P. Bour ,  Thomas R. Prunty ,  Linda Romano ,  Andrew P. Edwards ,  Isik C. Kizilyalli ,  Hui Nie ,  Richard J. Brown ,  Mahdan Raj

发明人： David P. Bour ,  Thomas R. Prunty ,  Linda Romano ,  Andrew P. Edwards ,  Isik C. Kizilyalli ,  Hui Nie ,  Richard J. Brown ,  Mahdan Raj

IPC分类号： H01L29/20 ,  H01L21/20

CPC分类号： H01L29/2003 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/2255 ,  H01L29/207 ,  H01L29/30 ,  H01L29/36 ,  H01L29/66204 ,  H01L29/8083 ,  H01L29/8611

摘要： A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.

摘要翻译： 半导体器件包括具有第一导电类型的III族氮化物衬底和与III族氮化物衬底电耦合的第一电极。 半导体器件还包括具有第二导电类型的III族氮化物材料，其在再生界面处与III族氮化物衬底耦合，并且p-n结设置在III族氮化物衬底和再生长界面之间。