公开(公告)号：US09075599B2

公开(公告)日：2015-07-07

申请号：US12894697

申请日：2010-09-30

申请人： Mark J. Hickey ,  Adam J. Muff ,  Matthew R. Tubbs ,  Charles D. Wait

发明人： Mark J. Hickey ,  Adam J. Muff ,  Matthew R. Tubbs ,  Charles D. Wait

IPC分类号： G06F9/345 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30098 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/345 ,  G06F9/3824

摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the most significant side of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.

摘要翻译： 由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的 具有诸如源破坏性操作等缺点的技巧。 所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数量的最低有效位连接到包含在指令中的每个寄存器地址部分的最高有效侧，从而产生完整寄存器地址，而不是提供完整寄存器 指令中使用的每个寄存器的地址宽度。 这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。 这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。

公开(公告)号：US20150178082A1

公开(公告)日：2015-06-25

申请号：US14562632

申请日：2014-12-05

申请人： Intel Corporation

发明人： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

公开(公告)号：US20150178079A1

公开(公告)日：2015-06-25

申请号：US14562609

申请日：2014-12-05

申请人： Intel Corporation

发明人： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

摘要翻译： 用于执行字符串比较操作的方法，装置和程序装置。 在一个实施例中，一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源分别存储对应于第一和第二文本串的第一和第二操作数的每个数据元素之间的比较结果。

公开(公告)号：US20150161053A1

公开(公告)日：2015-06-11

申请号：US14100356

申请日：2013-12-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： SANJEEV GHAI ,  GUY L. GUTHRIE ,  HUGH SHEN ,  DEREK E. WILLIAMS

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0833 ,  G06F12/0895 ,  G06F12/128

摘要： In response to receipt of a store-conditional (STCX) request of a processor core, the STCX request is buffered in an entry of a store queue for eventual service by a read-claim (RC) machine by reference to a cache array, and the STCX request is concurrently transmitted via a bypass path bypassing the store queue. In response to dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, the entry of the STCX request in the store queue is updated to prohibit selection of the STCX request in the store queue for service. In response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, the STCX is thereafter transmitted from the store queue to the dispatch logic and dispatched to the RC machine for service by reference to the cache array.

公开(公告)号：US09047199B2

公开(公告)日：2015-06-02

申请号：US14095385

申请日：2013-12-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0864 ,  G06F9/3824 ,  G06F12/0846 ,  G06F12/0855 ,  Y02D10/13

摘要： A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

摘要翻译： 提供了用于减少高速缓存访​​问操作的惩罚的计算机程序产品。 计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括分别将平台寄存器与高速缓存阵列相关联，将控制信息和关于一个或多个高速缓存阵列执行的存储操作的数据加载到分别与一个或多个缓存阵列中的一个或多个 缓存阵列，并且基于一个或多个缓存阵列变得可用，使用来自相同平台寄存器的控制信息将一个或多个平台寄存器中的数据提交到一个或多个缓存阵列。

公开(公告)号：US09047193B2

公开(公告)日：2015-06-02

申请号：US13520572

申请日：2011-01-28

申请人： Kenneth Chenghao Lin ,  Haoqi Ren

发明人： Kenneth Chenghao Lin ,  Haoqi Ren

IPC分类号： G06F9/34 ,  G06F12/08 ,  G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/34 ,  G06F9/355 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0802 ,  Y02D10/13

摘要： A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.

摘要翻译： 提供数字系统。 数字系统包括执行单元，零电平（L0）存储器和地址生成单元。 执行单元耦合到包含要在执行单元的操作中使用的数据的数据存储器。 L0存储器耦合在执行单元和数据存储器之间，并被配置为接收数据存储器中的一部分数据。 地址生成单元被配置为生成用于寻址L0存储器的地址信息。 此外，L0存储器使用来自地址生成单元的地址信息，将数据的一部分的单个指令的至少两个操作数直接提供给执行单元，而不将至少两个操作数加载到一个或多个寄存器中。

公开(公告)号：US20150106593A1

公开(公告)日：2015-04-16

申请号：US14576136

申请日：2014-12-18

申请人： Intel Corporation

发明人： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

公开(公告)号：US09003158B2

公开(公告)日：2015-04-07

申请号：US13656073

申请日：2012-10-19

申请人： Freescale Semiconductor, Inc.

发明人： William C. Moyer ,  Quyen Pho

IPC分类号： G06F12/02 ,  G06F12/04 ,  G06F9/30

CPC分类号： G06F12/04 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3834

摘要： A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

公开(公告)号：US20150095613A1

公开(公告)日：2015-04-02

申请号：US14502963

申请日：2014-09-30

申请人： ENYX SA

发明人： Edward KODDE

IPC分类号： G06F12/10 ,  G06F9/38 ,  G06F12/04

CPC分类号： G06F9/3824 ,  G06F21/71 ,  G06F21/79 ,  G06Q40/04 ,  H04L9/0894

摘要： An asset management method implemented on an integrated circuit uses a keys memory storing keys, each key being associated with an asset identifier, and a data memory storing asset information. The method comprises: receiving an input command for an asset comprising an asset identifier and asset information, computing addresses to Keys memory from the asset identifier, the computing addresses comprising calculating hashes from the asset identifier, finding or allocating an entry in keys memory for the asset, based on the computed set of addresses, depending on the input command, computing a data address to the data memory for the asset from the address and position in the keys memory at which an entry has been found or allocated for the asset; reading data in the data memory at the computed data address; and executing the input command based on the data read in the data memory at the data address.

摘要翻译： 在集成电路上实现的资产管理方法使用存储密钥的密钥存储器，每个密钥与资产标识符相关联，以及存储资产信息的数据存储器。 该方法包括：接收包括资产标识符和资产信息的资产的输入命令，从资产标识符计算到密钥存储器的地址，计算地址包括从资产标识符计算散列，在密钥存储器中找到或分配条目 资产，基于所计算的地址集合，取决于输入命令，从已经找到或分配给该资产的密钥存储器中的地址和位置计算资产的数据存储器的数据地址; 在计算的数据地址读取数据存储器中的数据; 并且基于在数据存储器中读取的数据在数据地址处执行输入命令。

公开(公告)号：US20150081987A1

公开(公告)日：2015-03-19

申请号：US14474711

申请日：2014-09-02

申请人： FUJITSU LIMITED ,  FUJITSU SEMICONDUCTOR LIMITED

发明人： Yi GE ,  Kazuo HORIO ,  Hiroshi HATANO

IPC分类号： G06F3/06 ,  G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/3824

摘要： An data supply circuit includes a buffer configured to store a plurality of data items each having a first width, a memory access unit configured to read source data stored in memory and to store the source data as one or more data items each having the first width in the buffer, and a selection control unit configured to repeat multiple times an operation of reading a data item having a second width shorter than or equal to the first width to read a plurality of data items each having the second width contiguously and sequentially from the buffer and configured to continue to read from a head end of the source data upon a read portion reaching a tail end of the source data.

摘要翻译： 数据提供电路包括：缓存器，被配置为存储每个具有第一宽度的多个数据项;存储器访问单元，被配置为读取存储在存储器中的源数据，并将源数据存储为每个具有第一宽度的一个或多个数据项 以及选择控制单元，被配置为重复多次读取具有小于或等于所述第一宽度的第二宽度的数据项的操作，以从所述第一宽度连续地和顺序地读取具有所述第二宽度的多个数据项 缓冲器并被配置为在读取部分到达源数据的尾端时继续从源数据的头端读取。