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    One-chip microcomputer and control method thereof as well as an IC card having such a one-chip microcomputer
    71.
    发明授权
    One-chip microcomputer and control method thereof as well as an IC card having such a one-chip microcomputer 有权
    单片机及其控制方法以及具有这种单片微型计算机的IC卡

    公开(公告)号：US06934884B1

    公开(公告)日：2005-08-23

    申请号：US09568683

    申请日：2000-05-11

    Applicant: Masaki Wakabayashi ,  Kazuhiro Yaegawa ,  Masaaki Tanno ,  Hiroki Suto ,  Tadao Takeda

    Inventor： Masaki Wakabayashi ,  Kazuhiro Yaegawa ,  Masaaki Tanno ,  Hiroki Suto ,  Tadao Takeda

    IPC: G06K19/07 ,  G01R31/3183 ,  G06F11/22 ,  G06F11/26 ,  G06F11/267 ,  G06F15/78 ,  G06F11/00

    CPC classification number: G01R31/318335 ,  G01R31/318385 ,  G01R31/318392 ,  G06F11/2236 ,  G06F11/2273

    Abstract: In order to provide a built-in self testing function, a one-chip microcomputer is equipped with an activation register for activating the test operation and a built-in self test activation pattern generator for setting initial values at test control circuits (pseudo random number generator, logical circuit testing compressor, pattern generator, and memory testing compressor). In accordance with an instruction from the CPU, a built-in self test is activated so that the results of tests of the memory and the group of logical circuits are read from the memory testing compressor and the logical circuit testing compressor, and respectively compared with expected values preliminarily stored in the memory in the one-chip microcomputer; thus, the results are diagnosed. Thus, it is possible to carry out a built-in self test without using a plurality of exclusively-used test terminals.

    Abstract translation: 为了提供内置的自检功能，单片机配备有用于激活测试操作的激活寄存器和内置的自检激活模式发生器，用于设置测试控制电路的初始值（伪随机数 发电机，逻辑电路测试压缩机，模式发生器和内存测试压缩机）。 根据CPU的指令，激活内置自检，使存储器和逻辑电路组的测试结果从存储器测试压缩器和逻辑电路测试压缩器读取，并分别与 初步存储在单片机中的存储器中的预期值; 因此，诊断结果。 因此，可以在不使用多个专用测试端子的情况下进行内置自检。

    Method and system for coding test pattern for scan design
    72.
    发明申请
    Method and system for coding test pattern for scan design 有权
    用于编码扫描设计测试图案的方法和系统

    公开(公告)号：US20040064771A1

    公开(公告)日：2004-04-01

    申请号：US10630957

    申请日：2003-07-30

    Applicant: International Business Machines Corporation

    Inventor： Joerg Georg Appinger ,  Michael Juergen Kessler ,  Manfred Schmidt

    IPC: G01R031/28

    CPC classification number: G01R31/318335 ,  G01R31/318385 ,  G01R31/318544 ,  G01R31/318566

    Abstract: A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.

    Abstract translation: 一种用于高效编码扫描设计中的IC测试图案和内置线性反馈移位寄存器（LFSR）的伪随机图案生成的方法和系统。 在初始化过程中，生成一个新的LFSR逻辑模型并将其集成到用于测试数据生成和测试向量压缩的系统中。 在测试数据生成过程中，使用LFSR逻辑模型指定和压缩测试向量。 测试向量中的每一个单独压缩。 然而，结果可以一次性地呈现，并且随后提供给用户或另一系统以便在待测试的集成电路中进一步处理或实现。 根据本发明，可以将包含例如多达500.000个移位寄存器的0/1值的测试向量（例如，大约50个所谓的关心位）压缩为小心位数的紧凑模式代码 ，即50位为50个关心位的例子。

    Test pattern compression for an integrated circuit test environment
    73.
    发明授权
    Test pattern compression for an integrated circuit test environment 有权

    公开(公告)号：US06543020B2

    公开(公告)日：2003-04-01

    申请号：US09947160

    申请日：2001-09-04

    Applicant: Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    Inventor： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    IPC: G06F1100

    CPC classification number: G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

    Abstract: A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

    Test vector compression method
    74.
    发明申请
    Test vector compression method 有权
    测试矢量压缩方法

    公开(公告)号：US20020162066A1

    公开(公告)日：2002-10-31

    申请号：US09802440

    申请日：2001-03-09

    Inventor： Ajay Khoche ,  Jochen Rivoir

    IPC: G06F011/00 ,  G01R031/28

    CPC classification number: G01R31/318335

    Abstract: A method of compressing a test vector creates a compressed test vector for use in conjunction with automated test equipment (ATE). The method comprises generating a test vector having a sequence of elements, at least one element of which comprises a nulldon't carenull value. A random sequence of elements is produced also. The test vector and the random sequence are segmented. Each segment of the test vector is compared to a corresponding segment of the random sequence to determine whether the corresponding segments match. When a match is found, a first flag value is sequentially inserted into a compression test vector. When a mismatch is found, a second flag value is sequentially inserted into the compression vector as well as the elements of the mismatched test vector segment. The compressed test vector may be decompressed according to the invention directly into a completely specified test vector using the flag values.

    Abstract translation: 压缩测试矢量的方法创建一个与自动测试设备（ATE）一起使用的压缩测试向量。 该方法包括生成具有元素序列的测试向量，其至少一个元素包括“不关心”值，还产生一个随机序列，测试向量和随机序列被分段，每个段 将测试矢量与随机序列的相应段进行比较，以确定相应的段是否匹配，当发现匹配时，将第一标记值顺序地插入到压缩测试向量中，当发现不匹配时，第二标志 值被顺序地插入到压缩向量以及不匹配的测试向量段的元素中。根据本发明，压缩的测试向量可以使用标志值直接解压缩成完全指定的测试向量。

    Parallel decompressor and related methods and apparatuses
    75.
    发明授权
    Parallel decompressor and related methods and apparatuses 失效
    并行解压缩器及相关方法及装置

    公开(公告)号：US5991909A

    公开(公告)日：1999-11-23

    申请号：US730066

    申请日：1996-10-15

    Applicant: Janusz Rajski ,  Jerzy Tyszer

    Inventor： Janusz Rajski ,  Jerzy Tyszer

    IPC: G01R31/3181 ,  G01R31/3183 ,  G01R31/28

    CPC classification number: G01R31/318335 ,  G01R31/31813 ,  G01R31/318385

    Abstract: A parallel decompressor capable of concurrently generating in parallel multiple portions of a deterministic partially specified data vector is disclosed. The parallel decompressor is also capable of functioning as a PRPG for generating pseudo-random data vectors. The parallel decompressor is suitable for incorporation into BIST circuitry of ICs. For BIST circuitry with multiple scan chains, the parallel decompressor may be incorporated without requiring additional flip-flops (beyond those presence in the LFSR and scan chains). In one embodiment, an incorporating IC includes boundary scan design compatible with the IEEE 1194.1 standard. Multiple ones of such ICs may be incorporated in a circuit board. Software tools for generating ICs with boundary scan having BIST circuitry incorporated with the parallel decompressor, and for computing the test data seeds for the deterministic partially specified test vectors are also disclosed.

    Abstract translation: 公开了能够同时并行地生成确定性部分指定的数据向量的多个部分的并行解压缩器。 并行解压缩器还能够用作生成伪随机数据向量的PRPG。 并行解压缩器适用于集成到IC的BIST电路中。 对于具有多个扫描链的BIST电路，可以并入并行解压缩器，而不需要额外的触发器（超出在LFSR和扫描链中的存在）。 在一个实施例中，并入IC包括与IEEE 1194.1标准兼容的边界扫描设计。 这些IC中的多个可以并入电路板中。 还公开了用于生成具有并入解压缩器的BIST电路的边界扫描的IC以及用于计算用于确定性部分指定的测试向量的测试数据种子的软件工具。

    In-line scan control apparatus for data processor testing
    76.
    发明授权
    In-line scan control apparatus for data processor testing 失效
    用于数据处理器测试的在线扫描控制装置

    公开(公告)号：US4718065A

    公开(公告)日：1988-01-05

    申请号：US845918

    申请日：1986-03-31

    Applicant: Richard F. Boyle ,  Leonard E. Overhouse

    Inventor： Richard F. Boyle ,  Leonard E. Overhouse

    IPC: G06F11/22 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/27 ,  G06F11/273 ,  G01R31/28

    CPC classification number: G01R31/318335 ,  G01R31/318385 ,  G01R31/318547 ,  G06F11/27 ,  G06F11/2733

    Abstract: Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data processor are designed for two-mode operation: A normal mode of operation during which they operate as a part of the data processor in normal fashion, and a scan mode operation during which the elemental storage units respond to scan control signals to form a number of shift register or scan line configurations for receiving the pseudo-random sequenced or non-random sequenced test patterns generated by the apparatus. During testing, the bit patterns are passed through the scan line configurations and applied to compression circuits where, using cyclic redundancy checking (CRC), compression bit patterns received from the scan lines are achieved. Produced are test signatures that are stored in a memory for later comparison with standardized signatures to determine the PASS/FAIL condition of the processor. Tests can be preceded and followed by a controlled scan of the digital logic to save and restore the operational state of the digital logic. In this manner, test interruptions are relatively unobtrusive and essentially transparent to the logic tested.

    Abstract translation: 公开了用于产生用于测试目的的应用于数据处理器或其它数字逻辑单元的伪随机位模式的装置。 根据本发明，数据处理器的某些元素存储单元（例如，触发器）被设计用于双模式操作：正常操作模式，其中它们以正常方式作为数据处理器的一部分操作，以及 扫描模式操作，其中元件存储单元响应于扫描控制信号以形成多个移位寄存器或扫描线配置，用于接收由该装置产生的伪随机排序或非随机排序的测试图案。 在测试期间，位模式通过扫描线配置并应用到压缩电路，其中使用循环冗余校验（CRC），实现从扫描线接收的压缩位模式。 产生的是存储在存储器中的测试签名，用于随后与标准化签名进行比较，以确定处理器的PASS / FAIL条件。 测试可以在数字逻辑之前和之后进行受控扫描，以保存和恢复数字逻辑的操作状态。 以这种方式，测试中断对于所测试的逻辑来说是相对不引人注目的并且基本上是透明的。

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