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    Test-time optimization with few slow scan pads
    2.
    发明授权
    Test-time optimization with few slow scan pads 有权

    公开(公告)号：US12203985B1

    公开(公告)日：2025-01-21

    申请号：US18222535

    申请日：2023-07-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Shalini Pathak ,  Pooja Jain

    IPC: G01R31/3185 ,  G01R31/317

    Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.

    COMPRESSION-BASED SCAN TEST SYSTEM
    3.
    发明申请
    COMPRESSION-BASED SCAN TEST SYSTEM 有权

    公开(公告)号：US20240393393A1

    公开(公告)日：2024-11-28

    申请号：US18322336

    申请日：2023-05-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Shalini Pathak ,  Prateek Singh

    IPC: G01R31/3181 ,  G01R31/3185

    Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.

    PARTIAL CHAIN RECONFIGURATION FOR TEST TIME REDUCTION
    5.
    发明申请
    PARTIAL CHAIN RECONFIGURATION FOR TEST TIME REDUCTION 有权

    公开(公告)号：US20250067803A1

    公开(公告)日：2025-02-27

    申请号：US18453045

    申请日：2023-08-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Shalini Pathak

    IPC: G01R31/3177

    Abstract: According to an embodiment, a first aspect relates to a method for testing a scan chain. The method includes segmenting the scan chain into two or more segments; adding a respective multiplexer at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between; asserting a select signal at a select terminal of the multiplexers such that a relative position of the two or more segments is rearranged positionally in a rearranged scan chain; generating a test pattern to be communicated to an input terminal of the rearranged scan chain and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result and an expected result.

    Redundancy circuit
    7.
    发明授权
    Redundancy circuit 有权

    公开(公告)号：US11848672B2

    公开(公告)日：2023-12-19

    申请号：US17719004

    申请日：2022-04-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Jeena Mary George

    IPC: H03K19/23 ,  G01R31/3185 ,  H03K19/20 ,  H03K19/00 ,  H03K3/037

    CPC classification number: H03K19/23 ,  G01R31/318525 ,  G01R31/318536 ,  H03K3/037 ,  H03K19/0021 ,  H03K19/20

    Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.

    REDUNDANCY CIRCUIT
    8.
    发明公开
    REDUNDANCY CIRCUIT 审中-公开

    公开(公告)号：US20230327674A1

    公开(公告)日：2023-10-12

    申请号：US17719004

    申请日：2022-04-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Jeena Mary George

    IPC: G01R31/3185 ,  H03K3/037 ,  H03K19/00 ,  H03K19/20

    CPC classification number: G01R31/318536 ,  H03K3/037 ,  H03K19/0021 ,  H03K19/20 ,  G01R31/318525

    Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.

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