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    PARTIAL CHAIN RECONFIGURATION FOR TEST TIME REDUCTION
    2.
    发明申请
    PARTIAL CHAIN RECONFIGURATION FOR TEST TIME REDUCTION 有权

    公开(公告)号：US20250067803A1

    公开(公告)日：2025-02-27

    申请号：US18453045

    申请日：2023-08-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Shalini Pathak

    IPC: G01R31/3177

    Abstract: According to an embodiment, a first aspect relates to a method for testing a scan chain. The method includes segmenting the scan chain into two or more segments; adding a respective multiplexer at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between; asserting a select signal at a select terminal of the multiplexers such that a relative position of the two or more segments is rearranged positionally in a rearranged scan chain; generating a test pattern to be communicated to an input terminal of the rearranged scan chain and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result and an expected result.

    Test-time optimization with few slow scan pads
    4.
    发明授权
    Test-time optimization with few slow scan pads 有权

    公开(公告)号：US12203985B1

    公开(公告)日：2025-01-21

    申请号：US18222535

    申请日：2023-07-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Shalini Pathak ,  Pooja Jain

    IPC: G01R31/3185 ,  G01R31/317

    Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.

    COMPRESSION-BASED SCAN TEST SYSTEM
    5.
    发明申请
    COMPRESSION-BASED SCAN TEST SYSTEM 有权

    公开(公告)号：US20240393393A1

    公开(公告)日：2024-11-28

    申请号：US18322336

    申请日：2023-05-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Sandeep Jain ,  Shalini Pathak ,  Prateek Singh

    IPC: G01R31/3181 ,  G01R31/3185

    Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.

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