公开(公告)号：US20150270129A1

公开(公告)日：2015-09-24

申请号：US14729262

申请日：2015-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chun Huang ,  Chih-Ming Lai ,  Ken-Hsien Hsieh ,  Ming-Feng Shieh

IPC分类号： H01L21/033 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/32

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a first pattern having a first feature of a first material on a semiconductor substrate. A second pattern with a second feature and third feature of a second material, interposed by the first feature, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the first feature, the second feature, and the third feature. After forming the spacer elements, the second material comprising the second and third features is selectively removed to form a first opening and a second opening. The first feature, the first opening and the second opening are used as a masking element to etch the target layer.

摘要翻译： 一种方法包括在半导体衬底上形成具有第一材料的第一特征的第一图案。 具有由第一特征插入的第二材料的第二特征和第三特征的第二图案形成在半导体衬底上。 间隔元件然后形成在第一特征，第二特征和第三特征的侧壁上。 在形成间隔元件之后，选择性地移除包括第二和第三特征的第二材料以形成第一开口和第二开口。 第一特征，第一开口和第二开口用作掩模元件以蚀刻目标层。

公开(公告)号：US20150082259A1

公开(公告)日：2015-03-19

申请号：US14552095

申请日：2014-11-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： HUANG-YU CHEN ,  Yuan-Te Hou ,  Yu-Hsiang Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F7/0035 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/12

摘要： A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.

摘要翻译： 布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束 出区。 目标图案应形成相应的主要特征和切割图案。

公开(公告)号：US08962464B1

公开(公告)日：2015-02-24

申请号：US14030601

申请日：2013-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ru-Gun Liu ,  Ken-Hsien Hsieh ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Tsai-Sheng Gau

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L27/088 ,  H01L21/28123 ,  H01L21/31053 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475

摘要： Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material.

摘要翻译： 本公开的实施例包括两层或更多层的自对准及其形成方法。 一个实施例是一种用于形成半导体器件的方法，包括在衬底上形成至少两个栅极，在所述至少两个栅极上形成至少两个对准结构，在所述至少两个对准结构上形成间隔物，以及在所述至少两个对准结构之间形成第一开口， 所述至少两个对准结构的一对，所述第一开口从所述基板的顶表面延伸第一距离。 该方法还包括用第一导电材料填充第一开口，在至少两个对准结构中的至少一个对准结构的间隔件之间形成第二开口，第二开口延伸离开衬底顶表面的第二距离，并填充 所述第二开口具有第二导电材料。

公开(公告)号：US20140322910A1

公开(公告)日：2014-10-30

申请号：US14331272

申请日：2014-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Po Tang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76838 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.

摘要翻译： 本公开提供了一种用于形成半导体器件的方法。 半导体器件包括设置在衬底上的第一导电线。 第一导线位于第一互连层中并沿着第一方向延伸。 半导体器件包括沿着与第一方向不同的第二方向延伸的第二导线和第三导线。 第二和第三导线位于与第一互连层不同的第二互连层中。 第二和第三导线被位于第一导电线之上或之下的间隙分开。 半导体器件包括将第二和第三导线电耦合在一起的第四导线。 第四导线位于与第一互连层和第二互连层不同的第三互连层中。

公开(公告)号：US20140252433A1

公开(公告)日：2014-09-11

申请号：US13911183

申请日：2013-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd .

发明人： Ming-Feng Shieh ,  Wen-Hung Tseng ,  Chih-Ming Lai ,  Ken-Hsien Hsieh ,  Tsai-Sheng Gau ,  Ru-Gun Liu

IPC分类号： H01L21/283 ,  H01L29/40

CPC分类号： H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41725

摘要： A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

摘要翻译： 一种用于在半导体器件内形成金属触点的方法包括：将第一层触点形成为围绕至少一个栅电极的第一电介质层，第一层触点延伸到下面的衬底的掺杂区域。 该方法还包括在第一电介质层上形成第二电介质层，并形成延伸穿过第二电介质层的第二层接触到第一层接触。