公开(公告)号：US20160005749A1

公开(公告)日：2016-01-07

申请号：US14321593

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Daniel Wayne PERRY

IPC: H01L27/115 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L27/11521 ,  G11C11/223 ,  G11C16/0433 ,  H01L27/11507 ,  H01L27/1159 ,  H01L28/56 ,  H01L29/40114 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7881

Abstract: Implementations of the technology described herein provide a Multiple Time Programmable (MTP) device, such as a Flash memory device, that implements a coupling gate in series with a floating gate. The coupling gate includes a ferroelectric capacitor and a conventional capacitor. The ferroelectric capacitor in combination with the coupling gate provides a negative capacitance such that the total capacitance of the combination of the floating gate and the coupling gate is larger than it would be if the coupling gate included only a conventional capacitor. One advantage of this device is that the effective coupling ratio between the coupling gate and the floating gate is increased. Another advantage is that the floating gate drops more voltage than conventional Multiple Time Programmable (MTP) devices.

Abstract translation: 本文描述的技术的实现提供了实现与浮动栅极串联的耦合门的多时间可编程（MTP）设备，诸如闪存设备。 耦合栅极包括铁电电容器和常规电容器。 铁电电容器与耦合栅极组合提供负电容，使得浮栅和耦合栅的组合的总电容大于如果耦合栅仅包括常规电容器的总电容。 该器件的一个优点是耦合栅极和浮置栅极之间的有效耦合比增加。 另一个优点是浮动栅极比传统的多时间可编程（MTP）器件降低了更多的电压。

公开(公告)号：US20150228795A1

公开(公告)日：2015-08-13

申请号：US14179311

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Chidi CHIDAMBARAM ,  Choh Fei YEAP

IPC: H01L29/78 ,  H03K17/687 ,  H01L29/66 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L29/7855 ,  H01L29/0607 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7851 ,  H03K17/687 ,  H03K2017/6878 ,  H03K2217/0018 ,  H03K2217/0054

Abstract: A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.

Abstract translation: 在FinFET的鳍通道下方具有背栅和阻挡层的FinFET，其中阻挡层的带隙大于背栅的带隙。 阻挡层在翅片通道下面用作蚀刻停止层，从而减少了翅片通道高度变化。 后门提供改进的电流控制。 由于较高的带隙阻挡层，穿孔较少。 FinFET还可以包括通过高带隙势垒层与源极/漏极扩散相邻的深埋入的应力源。

公开(公告)号：US20150028452A1

公开(公告)日：2015-01-29

申请号：US14512191

申请日：2014-10-10

Applicant: QUALCOMM INCORPORATED

Inventor： John J. ZHU ,  Bin YANG ,  PR CHIDAMBARAM ,  Lixin GE ,  Jihong CHOI

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的下互连层。 CBC结构还包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上部互连层和第二上部互连层之间的金属绝缘体金属（MIM）电容器层。 此外，CBC结构还包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。