公开(公告)号：US20210183005A1

公开(公告)日：2021-06-17

申请号：US16714052

申请日：2019-12-13

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chihong Zhang ,  Gang Zhong ,  Jian Jiang ,  Fei Wei ,  Minjie Huang ,  Zilin Ying ,  Yang Xia ,  Jing Han ,  Chun Yu ,  Eric Demers

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/50 ,  G06F9/30 ,  G06F1/03

Abstract: Methods, systems, and devices for graphic processing are described. The methods, systems, and devices may include or be associated with identifying a graphics instruction, determining that the graphics instruction is alias enabled for the device, partitioning an alias lookup table into one or more slots, allocating a slot of the alias lookup table based on the partitioning and determining that the graphics instruction is alias enabled, generating an alias instruction based on allocating the slot of the alias lookup table and determining that the graphics instruction is alias enabled, and processing the alias instruction.

公开(公告)号：US20210103852A1

公开(公告)日：2021-04-08

申请号：US16591353

申请日：2019-10-02

Applicant: QUALCOMM Incorporated

Inventor： Elina Kamenetskaya ,  Andrew Evan Gruber ,  Amir Momeni

IPC: G06N20/00 ,  G06T15/00 ,  G06F9/50

Abstract: Methods, systems, and devices for workload balancing for machine learning are described. Generally, a device may determine a size of a level one cache of a texture processor, identify a portion of input activation data for an iterative machine-learning process, and load the portion of input activation data into the level one cache. The device may allocate, based at least in part on a texture processor to shading processor arithmetic logic unit (ALU) resource ratio, a first set of one or more weight batches and a second set of one or more weight batches associated with the loaded portion of input activation data to the shading processor, and process the portion of input activation data based at least in part on the first set of one or more weight batches and the second set of one or more weight batches using the texture processor and the shading processor in parallel.

公开(公告)号：US10559123B2

公开(公告)日：2020-02-11

申请号：US13829900

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Andrew Evan Gruber

IPC: G06T15/00 ,  G06T15/80 ,  G06T17/20 ,  G06T15/50

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes designating a hardware shading unit of a graphics processing unit (GPU) to perform first shading operations associated with a first shader stage of a rendering pipeline. The process also includes switching operational modes of the hardware shading unit upon completion of the first shading operations. The process also includes performing, with the hardware shading unit of the GPU designated to perform the first shading operations, second shading operations associated with a second, different shader stage of the rendering pipeline.

公开(公告)号：US10062139B2

公开(公告)日：2018-08-28

申请号：US15218808

申请日：2016-07-25

Applicant: QUALCOMM Incorporated

Inventor： Maxim Kazakov ,  Andrew Evan Gruber

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: This disclosure describes examples of using two vertex shaders each one during different graphics processing passes in a binning architecture for graphics processing. A first vertex shader processes subset of attributes of a vertex in a binning pass, where the subset of attributes include those that contribute to visibility determination and attributes that may benefit from being processed with a vertex shader that provides functional flexibility. A second, different vertex shader processes another subset of attributes of the vertex in the rendering pass.

公开(公告)号：US20180025463A1

公开(公告)日：2018-01-25

申请号：US15218808

申请日：2016-07-25

Applicant: QUALCOMM Incorporated

Inventor： Maxim Kazakov ,  Andrew Evan Gruber

IPC: G06T1/20 ,  G06T15/80 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T15/80

Abstract: This disclosure describes examples of using two vertex shaders each one during different graphics processing passes in a binning architecture for graphics processing. A first vertex shader processes subset of attributes of a vertex in a binning pass, where the subset of attributes include those that contribute to visibility determination and attributes that may benefit from being processed with a vertex shader that provides functional flexibility. A second, different vertex shader processes another subset of attributes of the vertex in the rendering pass.

公开(公告)号：US20170316540A1

公开(公告)日：2017-11-02

申请号：US15141519

申请日：2016-04-28

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Lin Chen ,  Liang Li ,  Chunhui Mei

IPC: G06T1/20 ,  G06T15/80 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T2200/28

Abstract: A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.

公开(公告)号：US20170293995A1

公开(公告)日：2017-10-12

申请号：US15434851

申请日：2017-02-16

Applicant: QUALCOMM Incorporated

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Maurice Franklin Ribble ,  Andrew Evan Gruber

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/36

Abstract: A graphics processing unit (GPU) may rasterize a primitive into a plurality of samples, wherein vertices of the primitive are associated with VRS parameters. The GPU may determine a VRS quality group that comprises one or more sub regions of the plurality of samples based at least in part on the VRS parameters. The GPU may fragment shade a VRS tile that represents the VRS quality group, wherein the VRS tile comprises fewer samples than the VRS quality group. The GPU may amplify the stored VRS tile into shaded fragments that correspond to the VRS quality group.

公开(公告)号：US09747104B2

公开(公告)日：2017-08-29

申请号：US14275047

申请日：2014-05-12

Applicant: QUALCOMM Incorporated

Inventor： Lin Chen ,  Yun Du ,  Sumesh Udayakumaran ,  Chihong Zhang ,  Andrew Evan Gruber

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3012 ,  G06F9/30032 ,  G06F9/3017 ,  G06F9/3869 ,  G06F9/3875

Abstract: In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.

公开(公告)号：US09697580B2

公开(公告)日：2017-07-04

申请号：US14537589

申请日：2014-11-10

Applicant: QUALCOMM Incorporated

Inventor： Liang Li ,  Andrew Evan Gruber ,  Guofang Jiao ,  Zhenyu Qi ,  Gregory Steve Pitarys ,  Scott William Nolan

IPC: G06T1/20 ,  G09G5/18

CPC classification number: G06T1/20 ,  G09G5/18 ,  G09G2330/022

Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.

公开(公告)号：US09633411B2

公开(公告)日：2017-04-25

申请号：US14316391

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Lin Chen ,  Guofang Jiao ,  Chun Yu

IPC: G06T1/60 ,  G06T15/80 ,  G09G5/36

CPC classification number: G06T1/60 ,  G06T15/80 ,  G09G5/363 ,  G09G2352/00 ,  G09G2360/06

Abstract: Techniques are described for determining whether data of a variable for each of a plurality of graphics items is same. If determined that the data is the same, the techniques store the data in a storage location of a specialized shared general purpose register that is associated with the variable.