公开(公告)号：US20150324196A1

公开(公告)日：2015-11-12

申请号：US14275047

申请日：2014-05-12

Applicant: QUALCOMM Incorporated

Inventor： Lin Chen ,  Yun Du ,  Sumesh Udayakumaran ,  Chihong Zhang ,  Andrew Evan Gruber

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3012 ,  G06F9/30032 ,  G06F9/3017 ,  G06F9/3869 ,  G06F9/3875

Abstract: In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.

Abstract translation: 在一个示例中，一种方法包括响应于由处理单元接收一个或多个请求将第一值从第一通用寄存器（GPR）移动到第三GPR的指令，并且第二值从第二个 GPR到第四个GPR，由初始逻辑单元和在第一时钟周期期间将第一个值复制到初始流水线寄存器，通过初始逻辑复制第二个时钟周期，将第二个值复制到初始流水线寄存器 ，由最终逻辑单元和在第三时钟周期期间将第一值从最终流水线寄存器复制到第三GPR，并且由最终逻辑单元复制并在第四时钟周期期间从最终管道复制第二值 注册到第四个GPR。

公开(公告)号：US20180165786A1

公开(公告)日：2018-06-14

申请号：US15377498

申请日：2016-12-13

Applicant: QUALCOMM Incorporated

Inventor： Alexei Vladimirovich Bourd ,  Maxim Kazakov ,  Chunhui Mei ,  Sumesh Udayakumaran

IPC: G06T1/20 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first “host” shader to allow the first shader to execute “normally” on the GPU. The GPU may observe two sets of tasks, “guest” tasks. Based on, for example, detecting an availability of resources, the GPU may determine a “guest” task may be run while the “host” task is running. A second “guest” shader executes on a GPU by using resources that were configured for the first “host” shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.

公开(公告)号：US10026145B2

公开(公告)日：2018-07-17

申请号：US15377498

申请日：2016-12-13

Applicant: QUALCOMM Incorporated

Inventor： Alexei Vladimirovich Bourd ,  Maxim Kazakov ,  Chunhui Mei ,  Sumesh Udayakumaran

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first “host” shader to allow the first shader to execute “normally” on the GPU. The GPU may observe two sets of tasks, “guest” tasks. Based on, for example, detecting an availability of resources, the GPU may determine a “guest” task may be run while the “host” task is running. A second “guest” shader executes on a GPU by using resources that were configured for the first “host” shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.

公开(公告)号：US09747104B2

公开(公告)日：2017-08-29

申请号：US14275047

申请日：2014-05-12

Applicant: QUALCOMM Incorporated

Inventor： Lin Chen ,  Yun Du ,  Sumesh Udayakumaran ,  Chihong Zhang ,  Andrew Evan Gruber

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3012 ,  G06F9/30032 ,  G06F9/3017 ,  G06F9/3869 ,  G06F9/3875

Abstract: In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.

公开(公告)号：US09329867B2

公开(公告)日：2016-05-03

申请号：US14494240

申请日：2014-09-23

Applicant: QUALCOMM Incorporated

Inventor： Sumesh Udayakumaran ,  Se Jong Oh

IPC: G06F9/30 ,  G06F9/45

CPC classification number: G06F9/3013 ,  G06F8/441

Abstract: This disclosure describes techniques for allocating registers in a computing system that supports vector physical registers. The techniques for allocating registers may allocate physical registers to vector virtual registers based on priority information that is indicative of a relative importance of allocating respective vector virtual registers as vectors rather than scalars. The techniques for allocating registers may involve allocating physical registers to the vector virtual registers in an order that is determined based on the priority information. The techniques for allocating registers may further involve, in response to determining that no vector physical registers are available to assign to a vector virtual register, determining whether to perform vector-scalar live interval splitting for the vector virtual register, spill other register live intervals into a memory in order to allocate the vector virtual register as a vector, or assign scalar physical registers to the vector virtual register based on the priority information.

Abstract translation: 本公开描述了在支持向量物理寄存器的计算系统中分配寄存器的技术。 用于分配寄存器的技术可以基于指示将各个向量虚拟寄存器分配为向量而不是标量的相对重要性的优先级信息来将物理寄存器分配给向量虚拟寄存器。 用于分配寄存器的技术可以包括以基于优先级信息确定的顺序向物理寄存器分配物理寄存器。 用于分配寄存器的技术还可以响应于确定没有向量物理寄存器可用于分配给向量虚拟寄存器，确定是否对向量虚拟寄存器执行向量标量的实时间隔分割，将其他寄存器实时间隔溢出 存储器，以便将向量虚拟寄存器分配为向量，或者基于优先级信息将标量物理寄存器分配给向量虚拟寄存器。

公开(公告)号：US20150193234A1

公开(公告)日：2015-07-09

申请号：US14494240

申请日：2014-09-23

Applicant: QUALCOMM Incorporated

Inventor： Sumesh Udayakumaran ,  Se Jong Oh

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F8/441

Abstract: This disclosure describes techniques for allocating registers in a computing system that supports vector physical registers. The techniques for allocating registers may allocate physical registers to vector virtual registers based on priority information that is indicative of a relative importance of allocating respective vector virtual registers as vectors rather than scalars. The techniques for allocating registers may involve allocating physical registers to the vector virtual registers in an order that is determined based on the priority information. The techniques for allocating registers may further involve, in response to determining that no vector physical registers are available to assign to a vector virtual register, determining whether to perform vector-scalar live interval splitting for the vector virtual register, spill other register live intervals into a memory in order to allocate the vector virtual register as a vector, or assign scalar physical registers to the vector virtual register based on the priority information.

Abstract translation: 本公开描述了在支持向量物理寄存器的计算系统中分配寄存器的技术。 用于分配寄存器的技术可以基于指示将各个向量虚拟寄存器分配为向量而不是标量的相对重要性的优先级信息来将物理寄存器分配给向量虚拟寄存器。 用于分配寄存器的技术可以包括以基于优先级信息确定的顺序向物理寄存器分配物理寄存器。 用于分配寄存器的技术还可以包括响应于确定没有向量物理寄存器可用于分配给向量虚拟寄存器，确定是否对向量虚拟寄存器执行矢量标量的实时间隔分割，将其他寄存器实时间隔溢出 存储器，以便将向量虚拟寄存器分配为向量，或者基于优先级信息将标量物理寄存器分配给向量虚拟寄存器。