公开(公告)号：US10304689B2

公开(公告)日：2019-05-28

申请号：US15939677

申请日：2018-03-29

Applicant: International Business Machines Corporation

Inventor： Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Stuart A. Sieg ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/033

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers of the plurality of second spacers and a first set of mandrel structures of the plurality of mandrel structures. A second set of second spacers of the plurality of spacers and a second set of mandrel structures of the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.

公开(公告)号：US10249753B2

公开(公告)日：2019-04-02

申请号：US15814258

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Sivananda K. Kanakasabapathy ,  Jeffrey C. Shearer ,  Stuart A. Sieg ,  John R. Sporre ,  Junli Wang

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.

公开(公告)号：US20190088755A1

公开(公告)日：2019-03-21

申请号：US15803918

申请日：2017-11-06

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Fee Li Lie ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure si formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

公开(公告)号：US20190088754A1

公开(公告)日：2019-03-21

申请号：US15709902

申请日：2017-09-20

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Fee Li Lie ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure si formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

公开(公告)号：US20180331047A1

公开(公告)日：2018-11-15

申请号：US16041878

申请日：2018-07-23

Applicant: International Business Machines Corporation

Inventor： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L23/544 ,  H01L21/308 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  G03F9/00

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/708 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

公开(公告)号：US20180108752A1

公开(公告)日：2018-04-19

申请号：US15835906

申请日：2017-12-08

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/785

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US20180061942A1

公开(公告)日：2018-03-01

申请号：US15794636

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20180061941A1

公开(公告)日：2018-03-01

申请号：US15794616

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20180006150A1

公开(公告)日：2018-01-04

申请号：US15197996

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Sivananda K. Kanakasabapathy ,  Jeffrey C. Shearer ,  Stuart A. Sieg ,  John R. Sporre ,  Junli Wang

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/3065 ,  H01L21/033 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7827 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.

公开(公告)号：US09859224B2

公开(公告)日：2018-01-02

申请号：US15239166

申请日：2016-08-17

Applicant: International Business Machines Corporation

Inventor： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L21/311 ,  H01L23/544 ,  H01L21/308 ,  G03F7/20 ,  H01L21/033 ,  G03F9/00

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/708 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.