公开(公告)号：US20090114246A1

公开(公告)日：2009-05-07

申请号：US11933770

申请日：2007-11-01

Applicant: Nishant Sinha ,  Gurtej S. Sandhu

Inventor： Nishant Sinha ,  Gurtej S. Sandhu

IPC: B08B6/00 ,  B08B3/00

CPC classification number: B08B3/10 ,  B08B7/02 ,  B24C3/322 ,  B24C7/0007 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67051

Abstract: Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer layer may be formed across a surface. The dispersion may be directed toward the transfer layer, and the insolubles may impact the transfer layer. The impacting may generate force in the transfer layer, and such force may be transferred through the transfer layer to the surface. The surface may be a surface of a semiconductor substrate, and the force may be utilized to sweep contaminants from the semiconductor substrate surface. The transfer layer may be a liquid, and in some embodiments may be a cleaning solution.

Abstract translation: 一些实施方案包括用于处理表面的方法。 珠和/或其他不溶物可以分散在液体载体中以形成分散体。 可以跨越表面形成转印层。 分散体可以指向转移层，并且不溶物可能影响转移层。 冲击可能在转移层中产生力，并且这种力可以通过转移层转移到表面。 表面可以是半导体衬底的表面，并且该力可用于从半导体衬底表面扫除污染物。 转移层可以是液体，并且在一些实施方案中可以是清洁溶液。

公开(公告)号：US07498057B2

公开(公告)日：2009-03-03

申请号：US11075017

申请日：2005-03-08

Applicant: Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

Inventor： Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

IPC: C23C16/04

CPC classification number: C23C16/45519 ,  C23C16/4401 ,  C23C16/455

Abstract: A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.

Abstract translation: 沉积方法包括将基板定位在至少部分地由室壁限定的沉积室内。 所述室壁中的至少一个包括腔室表面，其中具有多个吹扫气体入口。 在衬底上设置工艺气体，有效地将层沉积到衬底上。 在这种提供过程中，材料粘附到室表面。 反应性净化气体从吹扫气体入口排出到沉积室，有效地在室表面上形成反应性气体帘幕并远离衬底，这种反应性气体与这种粘附材料反应。 考虑进一步的实现。

公开(公告)号：US07485526B2

公开(公告)日：2009-02-03

申请号：US11155197

申请日：2005-06-17

Applicant: Chandra Mouli ,  Gurtej S. Sandhu

Inventor： Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/7883 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/66825

Abstract: Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.

Abstract translation: 具有带有导电部分和电介质部分的浮动栅极的浮栅存储器单元便于浮置栅极内的电荷俘获位置的增加。 导电部分包括向浮动栅极提供体导电性的连续部件。 电介质部分在导电部分内是不连续的，并且可以包括介电材料岛和/或具有不连续性的一个或多个相邻的电介质材料层。

公开(公告)号：US07482653B2

公开(公告)日：2009-01-27

申请号：US11185320

申请日：2005-07-20

Applicant: Gurtej S. Sandhu ,  Chandra Mouli

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/788 ,  H01L29/76 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/42324 ,  B82Y10/00 ,  G11C13/025 ,  G11C16/0416 ,  G11C16/0483 ,  G11C2213/17 ,  G11C2213/75 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/511 ,  H01L29/7881 ,  H01L51/0048

Abstract: Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For some embodiments, the carbon nanotubes may be concentrated near the source/drain regions. For some embodiments, the tunnel dielectric layer may adjoin the substrate in at least a portion of the channel region.

Abstract translation: 具有插入在基板和隧道介电层之间的碳纳米管的浮栅存储器单元有助于将电荷弹入注入浮栅。 碳纳米管可以延伸穿过整个通道区域或沟道区域的一部分。 对于一些实施例，碳纳米管可以集中在源极/漏极区附近。 对于一些实施例，隧道介电层可以在沟道区域的至少一部分中与衬底相邻。

公开(公告)号：US07442977B2

公开(公告)日：2008-10-28

申请号：US11253461

申请日：2005-10-19

Applicant: Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

Inventor： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H01L27/108

CPC classification number: H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

Abstract: This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

公开(公告)号：US07432212B2

公开(公告)日：2008-10-07

申请号：US11490807

申请日：2006-07-20

Applicant: Jeffrey W. Honeycutt ,  Gurtej S. Sandhu

Inventor： Jeffrey W. Honeycutt ,  Gurtej S. Sandhu

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/0334

Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer comprising amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-comprising layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-comprising layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-comprising layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract translation: 本发明包括处理半导体衬底的方法。 在一个实施方式中，提供了具有外表面的半导体衬底。 这种表面具有围绕半导体衬底的周边边缘接收的周边区域。 包含无定形碳的层设置在衬底外表面上。 掩模层设置在无定形含碳层的外侧。 抗蚀剂层设置在掩模层的外侧。 外表面的周边区域的至少一部分包括无定形含碳层和抗蚀剂层，但基本上不含掩模层。 使用抗蚀剂层和掩模层对无定形含碳层进行图案化，以有效地在半导体衬底上形成掩模。 在图案化之后，半导体衬底通过掩模中形成的开口在掩模的内部进行处理。

公开(公告)号：US20080241386A1

公开(公告)日：2008-10-02

申请号：US12115412

申请日：2008-05-05

Applicant: Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

Inventor： Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

IPC: C23C16/08

CPC classification number: H01L21/32051 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45531 ,  C23C16/45534 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31616

Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

Abstract translation: 本发明包括在基板上形成沉积的组合物层的原子层沉积方法。 该方法包括将半导体衬底定位在原子层沉积室内。 在基材上形成中间体组合物单层，随后是与中间体组合物反应所需的沉积组合物，共同地将多个不同的组合物沉积前体流入沉积室内的基底。 材料粘附到室内部件表面，从而依次形成。 在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中，并有效地与这种粘附材料反应。 在反应气体流动之后，重复这种顺序形成。 考虑进一步的实现。

公开(公告)号：US07402489B2

公开(公告)日：2008-07-22

申请号：US11216415

申请日：2005-08-30

Applicant: Gurtej S. Sandhu ,  Pierre C. Fazan

Inventor： Gurtej S. Sandhu ,  Pierre C. Fazan

IPC: H01L21/8242

CPC classification number: H01L21/7687 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76895 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.

Abstract translation: 一种存储单元电容器和用于形成具有存储节点电极的存储单元电容器的方法，所述存储节点电极包括介于导电插塞和抗氧化层之间的阻挡层。 制造一层硅化钛以位于导电塞和抗氧化层之间。 绝缘层在具有高介电常数的介电层的沉积和退火期间保护阻挡层的侧壁。

公开(公告)号：US07396720B2

公开(公告)日：2008-07-08

申请号：US10899913

申请日：2004-07-27

Applicant: Sukesh Sandhu ,  Gurtej S. Sandhu

Inventor： Sukesh Sandhu ,  Gurtej S. Sandhu

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

Abstract: A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

Abstract translation: 第一电介质层形成在衬底上。 用作浮栅的单层第一导电层形成在第一介电层上。 在第一导电层中形成槽，以增加浮栅与控制栅的电容耦合。 在浮栅层上形成隔间介电层。 在第二介电层上形成第二导电层以用作控制栅极。

公开(公告)号：US20080121976A1

公开(公告)日：2008-05-29

申请号：US11513933

申请日：2006-08-31

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L29/788 ,  H01L21/04 ,  H01L29/68 ,  G11C11/34

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。