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    Global interrupt and barrier networks
    71.
    发明授权
    Global interrupt and barrier networks 失效
    全局中断和屏障网络

    公开(公告)号：US07444385B2

    公开(公告)日：2008-10-28

    申请号：US10468997

    申请日：2002-02-25

    Applicant: Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken

    Inventor： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E Giampapa ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken

    IPC: G06F15/16

    CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

    Abstract: A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.

    Abstract translation: 一种用于在计算结构中产生全局异步信号的系统和方法。 特别地，实现了全局中断和屏障网络，其实现用于根据处理算法产生用于控制由计算结构的选定处理节点处理元件执行的全局异步操作的全局中断和屏障信号的逻辑; 并且包括用于经由低延迟路径将全局中断和屏障信号传送到元件的处理节点的物理互连。 全局异步信号分别在处理节点处启动中断和屏障操作，这些时间被选择用于优化处理算法的性能。 在一个实施例中，全局中断和屏障网络在可扩展的大规模并行超级计算设备结构中实现，该结构包括由多个独立网络互连的多个处理节点，每个节点包括用于根据需要执行计算或通信活动的一个或多个处理元件 当执行并行算法操作时。 一个多个独立网络包括全局树网络，用于在全球树网络节点或其子树之间实现高速全局树通信。 全局中断和屏障网络可以与全局树网络并行操作，以提供全局异步边带信号。

    Through board stacking of multiple LGA-connected components
    75.
    发明申请
    Through board stacking of multiple LGA-connected components 有权
    通过板堆叠多个LGA连接的组件

    公开(公告)号：US20080054430A1

    公开(公告)日：2008-03-06

    申请号：US11511815

    申请日：2006-08-29

    Applicant: Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

    Inventor： Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

    IPC: H01L23/02

    CPC classification number: H05K3/325 ,  H05K2201/0314 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2018

    Abstract: A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.

    Abstract translation: 提供了一种封装设计，其中芯片模块通过PCB顶表面上的焊盘网格阵列（LGA）连接到印刷电路板（PCB），并且电源通过第二个LGA连接到PCB PCB的底面。 芯片模块，电源和LGA的堆叠被保持就位并用致动硬件压缩形成可调节的框架。 该封装允许模块或PS的现场可替代性，并提供从PS到模块的最短可能布线距离，从而实现更高的性能。

    Fault isolation through no-overhead link level CRC
    77.
    发明授权
    Fault isolation through no-overhead link level CRC 失效
    通过无架空链路级CRC进行故障隔离

    公开(公告)号：US07210088B2

    公开(公告)日：2007-04-24

    申请号：US10468996

    申请日：2002-02-25

    Applicant: Dong Chen ,  Paul W. Coteus ,  Alan G. Gara

    Inventor： Dong Chen ,  Paul W. Coteus ,  Alan G. Gara

    IPC: G06F11/00 ,  G06F13/00 ,  G06F7/02 ,  H03M13/00

    CPC classification number: H03M13/091 ,  G11B20/1833 ,  H04L1/0061

    Abstract: A fault isolation technique for checking the accuracy of data packets transmitted between nodes of a parallel processor. An independent crc is kept of all data sent from one processor to another, and received from one processor to another. At the end of each checkpoint, the crcs are compared. If they do not match, there was an error. The crcs may be cleared and restarted at each checkpoint. In the preferred embodiment, the basic functionality is to calculate a CRC of all packet data that has been successfully transmitted across a given link. This CRC is done on both ends of the link, thereby allowing an independent check on all data believed to have been correctly transmitted. Preferably, all links have this CRC coverage, and the CRC used in this link level check is different from that used in the packet transfer protocol. This independent check, if successfully passed, virtually eliminates the possibility that any data errors were missed during the previous transfer period.

    Abstract translation: 用于检查并行处理器节点之间传输的数据包的精度的故障隔离技术。 保持从一个处理器发送到另一个处理器的所有数据的独立crc，并从一个处理器接收另一个处理器。 在每个检查点的末尾，比较crcs。 如果它们不匹配，则出现错误。 可以在每个检查点清除并重新启动crcs。 在优选实施例中，基本功能是计算已经通过给定链路成功发送的所有分组数据的CRC。 该CRC在链路的两端完成，从而允许对所有被认为已被正确发送的数据进行独立的检查。 优选地，所有链路具有该CRC覆盖，并且在该链路级检查中使用的CRC与在分组传送协议中使用的不同。 这种独立检查，如果成功通过，几乎消除了在以前的传输期间错过任何数据错误的可能性。

    Circuit and method for reading data transfers that are sent with a source synchronous clock signal
    78.
    发明授权
    Circuit and method for reading data transfers that are sent with a source synchronous clock signal 失效
    用于读取与源同步时钟信号一起发送的数据传输的电路和方法

    公开(公告)号：US06807125B2

    公开(公告)日：2004-10-19

    申请号：US10225871

    申请日：2002-08-22

    Applicant: Paul W. Coteus ,  Frank D. Ferraiolo ,  Kevin C. Gower

    Inventor： Paul W. Coteus ,  Frank D. Ferraiolo ,  Kevin C. Gower

    IPC: G11C1100

    CPC classification number: G11C7/106 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066

    Abstract: A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.

    Abstract translation: 用于读取与源同步时钟信号一起发送的数据传输的电路和方法。 该电路具有数据输入端，用于接收承载传送数据的数据信号，用于接收同步时钟信号的时钟输入端和连接到时钟输入端的延迟电路，用于产生从所述同步时钟信号延迟预定时间的延迟时钟信号 期。 电路还包括连接到数据输入端的流水线，用于响应于所述延迟的时钟信号对数据输入上的数据进行采样，从而延伸输入数据的采样。

    Memory and system configuration for programming a redundancy address in an electric system
    79.
    发明授权
    Memory and system configuration for programming a redundancy address in an electric system 有权
    用于编程电气系统中冗余地址的存储器和系统配置

    公开(公告)号：US06178126B1

    公开(公告)日：2001-01-23

    申请号：US09534423

    申请日：2000-03-23

    Applicant: Toshiaki Kirihata ,  Paul W. Coteus ,  Warren E. Maule ,  Steven Tomashot

    Inventor： Toshiaki Kirihata ,  Paul W. Coteus ,  Warren E. Maule ,  Steven Tomashot

    IPC: G11C1300

    CPC classification number: G11C29/72 ,  G11C29/785

    Abstract: A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices. Therein, the relation between the system memory data bus and the memory data ports for the memory devices are recognized by a memory controller. A microprocessor in the electric system is used for testing the memories and for analyzing the redundancy address. The present invention further includes a post device identification protocol to effectively debug field problems.

    Abstract translation: 多个存储设备中的冗余地址由电气系统中可用的至少两种协议来识别。 第一个协议是模式寄存器设置命令（或扩展模式寄存器设置命令）。 芯片选择信号确定多个存储器模块中的一个，其中存储器件被识别为具有至少一个数据端口。 或者，可以优选地使用数据选通端口或数据掩码端口来选择存储设备，而不是使用数据端口。 第二协议是RAM访问命令，其通过多个地址端口（ADR）识别所选择的RAM内的有缺陷的存储器单元地址（冗余地址）。 通过电可编程熔丝或集成在每个存储器中的动态可编程冗余锁存器实现冗余地址编程方法。 电气系统配置优选地包括用于存储用于存储器件的数据端口组织的非易失性存储设备。 其中，存储器控制器识别系统存储器数据总线与存储器件的存储器数据端口之间的关系。 电气系统中的微处理器用于测试存储器和分析冗余地址。 本发明还包括有效调试现场问题的后期设备识别协议。

    Secure viewing of display units using an electronic shutter
    80.
    发明授权
    Secure viewing of display units using an electronic shutter 失效
    使用电子快门查看显示单元

    公开(公告)号：US5614920A

    公开(公告)日：1997-03-25

    申请号：US342953

    申请日：1994-11-21

    Applicant: Paul W. Coteus ,  Douglas S. Goodman

    Inventor： Paul W. Coteus ,  Douglas S. Goodman

    IPC: G06F1/00 ,  G06F21/00 ,  G09G5/00

    CPC classification number: G06F21/84 ,  H04N13/0438 ,  H04N2013/0463

    Abstract: Apparatus for masking a displayed image by merging it with a second featureless image made of short pulses of light that are introduced into a transparent screen disposed between the display and the viewer. An electronic shutter timed to match the sequence of the masking light pulses separates or blocks the masking image to permit the primary image to be viewed only by the person having the electronic shutter.

    Abstract translation: 用于通过将显示图像与由引导到布置在显示器和观看者之间的透明屏幕的短脉冲光构成的第二无特征图像进行合并来掩蔽所显示的图像的装置。 定时匹配屏蔽光脉冲序列的电子快门分离或阻挡掩蔽图像，以允许仅由具有电子快门的人观看主图像。

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